A new analytical approach to estimate the effects of SEUs in TMR architectures implemented through SRAM-based FPGAs

✍ Scribed by Sterpone, L.; Violante, M.

• Book ID: 118002454
• Publisher: IEEE
• Year: 2005
• Tongue: English
• Weight: 178 KB
• Volume: 52
• Category: Article
• ISSN: 0018-9499
• DOI: 10.1109/tns.2005.860745