✦ LIBER ✦

Analysis and design of high-speed and low-power CMOS PLAs

✍ Scribed by Jinn-Shyan Wang; Ching-Rong Chang; Chingwei Yeh

Book ID: 119775922
Publisher: IEEE
Year: 2001
Tongue: English
Weight: 414 KB
Volume: 36
Category: Article
ISSN: 0018-9200
DOI: 10.1109/4.938375

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

High-speed and low-power CMOS priority e

High-speed and low-power CMOS priority encoders

✍ Jinn-Shyan Wang; Chung-Hsun Huang 📂 Article 📅 2000 🏛 IEEE 🌐 English ⚖ 169 KB

Circuit Design of a High Speed and Low P

Circuit Design of a High Speed and Low Power CMOS Continuous-time Current Comparator

✍ Lu Chen; Bingxue Shi; Chun Lu 📂 Article 📅 2001 🏛 Springer 🌐 English ⚖ 78 KB

An automated, low power, high speed comp

An automated, low power, high speed complementary PLA design system for VLSI applications

✍ S. Powell; E. Iodice; E. Friedman 📂 Article 📅 1984 🏛 Elsevier Science 🌐 English ⚖ 507 KB

An automated Programmable Logic Array (PLA) design system that is fully compatible with the density and power constraints of VLSI is described. A low power CMOS version of the PLA has been integrated into a technology independent, automated PLA generation system to provide a self-contained, highly f

Variable supply-voltage scheme for low-p

Variable supply-voltage scheme for low-power high-speed CMOS digital design

✍ Kuroda, T.; Suzuki, K.; Mita, S.; Fujita, T.; Yamane, F.; Sano, F.; Chiba, A.; W 📂 Article 📅 1998 🏛 IEEE 🌐 English ⚖ 331 KB

A high speed and low power on CMOS/SOI t

A high speed and low power on CMOS/SOI technology

✍ Lee, M.; Fujishima, M.; Asada, K. 📂 Article 📅 1993 🏛 IEEE 🌐 English ⚖ 274 KB

Design and Application of Power Optimize

Design and Application of Power Optimized High-Speed CMOS Frequency Dividers

✍ Henzler, S.; Koeppe, S. 📂 Article 📅 2008 🏛 IEEE 🌐 English ⚖ 646 KB