✦ LIBER ✦

Circuit Design of a High Speed and Low Power CMOS Continuous-time Current Comparator

✍ Scribed by Lu Chen; Bingxue Shi; Chun Lu

Book ID: 110299119
Publisher: Springer
Year: 2001
Tongue: English
Weight: 78 KB
Volume: 28
Category: Article
ISSN: 0925-1030
DOI: 10.1023/a:1011260111919

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

A novel low-power, low-offset, and high-

A novel low-power, low-offset, and high-speed CMOS dynamic latched comparator

✍ HeungJun Jeon; Yong-Bin Kim 📂 Article 📅 2011 🏛 Springer 🌐 English ⚖ 748 KB

A high-speed, low-power SOI CMOS circuit

A high-speed, low-power SOI CMOS circuit with variable threshold voltages

✍ Hisayuki Higuchi; Takahide Ikeda 📂 Article 📅 2001 🏛 John Wiley and Sons 🌐 English ⚖ 276 KB

Bandwidth optimization of a low power, h

Bandwidth optimization of a low power, high speed CMOS current op amp

✍ Erik Bruun 📂 Article 📅 1995 🏛 Springer 🌐 English ⚖ 809 KB

A Wired-AND Current-Mode Logic Circuit T

A Wired-AND Current-Mode Logic Circuit Technique in CMOS for Low-Voltage, High-Speed and Mixed-Signal VLSIC

✍ Ismail Enis Ungan; Murat Acskar 📂 Article 📅 1997 🏛 Springer 🌐 English ⚖ 140 KB

Use of multiple-valued logic with 1.9-V

Use of multiple-valued logic with 1.9-V operational power supply to obtain a high-speed current-mode logic circuit

✍ Yasuhiro Sugimoto 📂 Article 📅 1996 🏛 John Wiley and Sons 🌐 English ⚖ 635 KB

This paper proposes a new construction of bipolar current-mode (CML) logic circuits based on the multiple-valued logic concept. Applying the multiple-valued logic concept, the new logic function, which can replace the conventional stack logic circuit and can be operated by a low supply voltage, can