✦ LIBER ✦

An optimized output stage for MOS integrated circuits

✍ Scribed by Linholm, L.W.

Book ID: 119797378
Publisher: IEEE
Year: 1975
Tongue: English
Weight: 344 KB
Volume: 10
Category: Article
ISSN: 0018-9200
DOI: 10.1109/jssc.1975.1050569

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

Comments on "An optimized output stage f

Comments on "An optimized output stage for MOS integrated circuits" [with reply]

✍ Jaeger, R.C.; Linholm, L.W. 📂 Article 📅 1975 🏛 IEEE 🌐 English ⚖ 347 KB

Analog MOS integrated circuits for signa

Analog MOS integrated circuits for signal processing

✍ Sedra, A.S. 📂 Article 📅 1987 🏛 IEEE 🌐 English ⚖ 107 KB

Optimized ESD protection circuits for hi

Optimized ESD protection circuits for high-speed MOS/VLSI

✍ Fujishin, E.; Garrett, K.; Levis, M.P.; Motta, R.F.; Hartranft, M. 📂 Article 📅 1985 🏛 IEEE 🌐 English ⚖ 540 KB

Fabrication of an integrated microprobin

Fabrication of an integrated microprobing head for fault analysis of mos integrated circuits

✍ Shuichi Shoji; Masayoshi Esashi; Tadayuki Matsuo 📂 Article 📅 1988 🏛 Elsevier Science ⚖ 981 KB

Integrated MOS distributed RC networks f

Integrated MOS distributed RC networks for frequency selective circuits

✍ S.M. Bozic; C.A. Miller; R.I. Salawu 📂 Article 📅 1973 🏛 Elsevier Science 🌐 English ⚖ 328 KB

Improved neuron MOS-transistor structure

Improved neuron MOS-transistor structures for integrated neural network circuits

✍ Rantala, A.; Franssila, S.; Kaski, K.; Lampinen, J.; Aberg, M.; Kuivalainen, P. 📂 Article 📅 2001 🏛 The Institution of Electrical Engineers 🌐 English ⚖ 915 KB