An experimental 2-bit/cell storage DRAM for macro cell or memory-on-logic application: T Furuyama, T Ohsawa (Toshiba Corp., Kawasaki, Japan), Y Nagahama, H Tanaka, Y Watanabe, T Kimura, K Muraoka, K Natori Proceedings of the IEEE 1988 Custom Integrated Circuits Conference (Cat. No. 88CH2584-1), Rochester, NY, USA, 16–19 May 1988 (New York, NY, USA: IEEE 1988), pp. 4.4/1–4

A 185 K×6 field memory for TV/VTR pictur

A 185 K×6 field memory for TV/VTR pictures: Y Murakami, T Imai, K Inoue, K Hattori, Y Matsuura, M Hayashi, K Miki, Y Torimaru (Sharp. Corp., Nara, Japan) Proceedings of the IEEE 1988 Custom Integrated Circuits Conference (Cat. No. 88CH2584-1), Rochester, NY, USA, 16–19 May 1988 (New York, NY, USA: IEEE 1988), pp. 4.5/1–4

📂 Article 📅 1988 🏛 Elsevier Science 🌐 English ⚖ 100 KB

A testable design of dynamic random-access memory (DRAM) architecture which allows one to access multiple cells in a word line simultaneously is presented. The technique utilises the two-dimensional (2-D) organisation of the DRAM and the resulting speedup of the conventional algorithm is considerabl

Wide operating voltage range and low pow

Wide operating voltage range and low power consumption EPROM structure for consumer oriented ASIC applications: T Maruyama, Y Kawamura, N Kitagawa, K Shinada, N Hanada, Y Suzuki (Toshiba Semicond. Syst. Eng. Center, Kawasaki, Japan) Proceedings of the IEEE 1988 Custom Integrated Circuits Conference (Cat. No. 88CH2584-1), Rochester, NY, USA, 16–19 May 1988 (New York, NY, USA: IEEE 1988), pp. 4.1/1−4

📂 Article 📅 1988 🏛 Elsevier Science 🌐 English ⚖ 99 KB

A testable design of dynamic random-access memory (DRAM) architecture which allows one to access multiple cells in a word line simultaneously is presented. The technique utilises the two-dimensional (2-D) organisation of the DRAM and the resulting speedup of the conventional algorithm is considerabl

A 4 nsec 4 K×1 bit two-port BiCMOS SRAM:

A 4 nsec 4 K×1 bit two-port BiCMOS SRAM: T S Yang, M A Horowitz, B A Wooley (Center for Integrated Syst., Stanford Univ., CA, USA) Proceedings of the IEEE 1988 Custom Integrated Circuits Conference (Cat. No. 88CH2584-1), Rochester, NY, USA, 16–19 May 1988 (New York, NY, USA: IEEE 1988), pp. 4.7/1–4

📂 Article 📅 1988 🏛 Elsevier Science 🌐 English ⚖ 87 KB

The authors introduce a two-port BiCMOS (bipolar complementary metal-oxide semiconductor) static memory cell that combines ECL (emitter-coupledlogic)-level word-line voltage swings and emitterfollower bit line coupling with a static CMOS latch to achieve access times comparable to those of highspeed