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The authors introduce a two-port BiCMOS (bipolar complementary metal-oxide semiconductor) static memory cell that combines ECL (emitter-coupledlogic)-level word-line voltage swings and emitterfollower bit line coupling with a static CMOS latch to achieve access times comparable to those of highspeed bipolar SRAMs (static random-access memories), preserving the high density and low power of CMOS memory arrays. The memory can be accessed for read and write independently and simultaneously, making it especially attractive for the design of video, cache, and other application-specific memories. An experimental 4 K• bit two-port memory integrated in a 1.5 !am-5 GHz BiCMOS technology exhibits a read access time of 4 ns and a power dissipation of 550 mW. (4 refs.
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A testable design of dynamic random-access memory (DRAM) architecture which allows one to access multiple cells in a word line simultaneously is presented. The technique utilises the two-dimensional (2-D) organisation of the DRAM and the resulting speedup of the conventional algorithm is considerabl
A testable design of dynamic random-access memory (DRAM) architecture which allows one to access multiple cells in a word line simultaneously is presented. The technique utilises the two-dimensional (2-D) organisation of the DRAM and the resulting speedup of the conventional algorithm is considerabl