Wide operating voltage range and low power consumption EPROM structure for consumer oriented ASIC applications: T Maruyama, Y Kawamura, N Kitagawa, K Shinada, N Hanada, Y Suzuki (Toshiba Semicond. Syst. Eng. Center, Kawasaki, Japan) Proceedings of the IEEE 1988 Custom Integrated Circuits Conference (Cat. No. 88CH2584-1), Rochester, NY, USA, 16–19 May 1988 (New York, NY, USA: IEEE 1988), pp. 4.1/1−4

• Publisher: Elsevier Science
• Year: 1988
• Tongue: English
• Weight: 99 KB
• Volume: 19
• Category: Article
• ISSN: 0026-2692
• DOI: 10.1016/s0026-2692(88)80011-9

✦ Synopsis

A testable design of dynamic random-access memory (DRAM) architecture which allows one to access multiple cells in a word line simultaneously is presented. The technique utilises the two-dimensional (2-D) organisation of the DRAM and the resulting speedup of the conventional algorithm is considerable. The failure mechanism in the three-dimensional (3-D) DRAM with trench-type capacitor is specifically investigated. As opposed to the earlier approaches for testing parametric faults that used sliding diagonaltype tests with O(n 3/2) complexity, the algorithms discussed here are different and have O(v/n/p) complexity, wherep is the number ofsubarrays within the DRAM chip. These algorithms can be applied externally from the chip and also they can be easily generated for built-in self-test applications. (12 refs.