✦ LIBER ✦

An Automated BIST Architecture for Testing and Diagnosing FPGA Interconnect Faults

✍ Scribed by Jack Smith; Tian Xia; Charles Stroud

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

Testing and diagnosis of interconnect fa

✍ Harris, I.G.; Tessier, R. 📂 Article 📅 2002 🏛 IEEE 🌐 English ⚖ 358 KB

An Efficient BIST Architecture for Delay

✍ Patrick Girard; Olivier Héron; Serge Pravossoudovitch; Michel Renovell 📂 Article 📅 2006 🏛 Springer US 🌐 English ⚖ 855 KB

Techniques and algorithms for fault grad

✍ Tahoori, M.B.; Mitra, S. 📂 Article 📅 2004 🏛 IEEE 🌐 English ⚖ 740 KB

[IEEE 2012 Design, Automation & Test in

✍ Bolchini, C.; Miele, A.; Sciuto, D. 📂 Article 📅 2012 🏛 IEEE ⚖ 276 KB

[IEEE 2012 IEEE International Test Confe

✍ Sadeghi-Kohan, Somayeh; Namaki-Shoushtari, Majid; Javaheri, Fatemeh; Navabi, Zai 📂 Article 📅 2012 🏛 IEEE ⚖ 435 KB

[IEEE 2008 Design, Automation and Test i

✍ Alt, Nicolas; Claus, Christopher; Stechele, Walter 📂 Article 📅 2008 🏛 IEEE ⚖ 403 KB