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Algorithm and architecture for a high density, low power scalar product macrocell

โœ Scribed by Gu, J.; Chang, C.-H.; Yeo, K.-S.

Book ID
114448587
Publisher
The Institution of Electrical Engineers
Year
2004
Tongue
English
Weight
928 KB
Volume
151
Category
Article
ISSN
1350-2387

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A low power dissipation architecture of
A low power dissipation architecture of high-performance multiprocessor for state-space digital filters using block-state realization
โœ Yoshitaka Tsunekawa; Michiru Iwawaki; Mamoru Miura ๐Ÿ“‚ Article ๐Ÿ“… 2000 ๐Ÿ› John Wiley and Sons ๐ŸŒ English โš– 322 KB ๐Ÿ‘ 2 views

In this paper, a low power dissipation architecture of high-performance multiprocessor is proposed for statespace digital filters using block-state realization in order to realize high-accuracy, high-speed process with reduced hardware previously proposed by the authors. Distributed arithmetic is ap