In this paper, a low power dissipation architecture of high-performance multiprocessor is proposed for statespace digital filters using block-state realization in order to realize high-accuracy, high-speed process with reduced hardware previously proposed by the authors. Distributed arithmetic is applied to this high-performance VLSI processor so that a high sampling rate can be maintained even at a higher-order filter. Further, in the proposed method, the function generation of the distributed arithmetic carried out previously by ROM is now realized with the optimum function circuit using logic gates. Hence, the redundancy of the function can be eliminated so that a substantial reduction in power dissipation is possible. Also, by taking into account the filter configuration and system configuration based on the nature of this circuit, the power consumption of the entire multiprocessor system with a multirate nature can be reduced even further. As a result, in the case where 0.6-Pm CMOS standard cells (with a power supply voltage of 5 V) are used, an extremely high sampling rate of 188.2 MHz (for a block length of 48) can be obtained in a higher-order filter of order 16. In addition, the power consumption of the entire multiprocessor system is as low as about 29% of the case when the distributed arithmetic is realized with ROM.