Advanced VLSI Design and Testability Issues

✍ Scribed by Suman Lata Tripathi (editor), Sobhit Saxena (editor), Sushanta Kumar Mohapatra (editor)

• Publisher: CRC Press
• Year: 2020
• Tongue: English
• Leaves: 379
• Edition: 1
• Category: Library

✦ Synopsis

This book facilitates the VLSI-interested individuals with not only in-depth knowledge, but also the broad aspects of it by explaining its applications in different fields, including image processing and biomedical. The deep understanding of basic concepts gives you the power to develop a new application aspect, which is very well taken care of in this book by using simple language in explaining the concepts. In the VLSI world, the importance of hardware description languages cannot be ignored, as the designing of such dense and complex circuits is not possible without them. Both Verilog and VHDL languages are used here for designing. The current needs of high-performance integrated circuits (ICs) including low power devices and new emerging materials, which can play a very important role in achieving new functionalities, are the most interesting part of the book. The testing of VLSI circuits becomes more crucial than the designing of the circuits in this nanometer technology era. The role of fault simulation algorithms is very well explained, and its implementation using Verilog is the key aspect of this book.

This book is well organized into 20 chapters. Chapter 1 emphasizes on uses of FPGA on various image processing and biomedical applications. Then, the descriptions enlighten the basic understanding of digital design from the perspective of HDL in Chapters 2–5. The performance enhancement with alternate material or geometry for silicon-based FET designs is focused in Chapters 6 and 7. Chapters 8 and 9 describe the study of bimolecular interactions with biosensing FETs. Chapters 10–13 deal with advanced FET structures available in various shapes, materials such as nanowire, HFET, and their comparison in terms of device performance metrics calculation. Chapters 14–18 describe different application-specific VLSI design techniques and challenges for analog and digital circuit designs. Chapter 19 explains the VLSI testability issues with the description of simulation and its categorization into logic and fault simulation for test pattern generation using Verilog HDL. Chapter 20 deals with a secured VLSI design with hardware obfuscation by hiding the IC’s structure and function, which makes it much more difficult to reverse engineer.

✦ Table of Contents

Cover
Half Title
Title Page
Copyright Page
Table of Contents
Preface to the First Edition
Editors
Contributors
Chapter 1 Digital Design with Programmable Logic Devices
1.1 Introduction
1.2 Factory-Programmable Devices
1.3 Read-Only Memory
1.4 Programmable Read-Only Memory
1.5 Erasable Programmable Read-Only Memory
1.6 Electrically Erasable Programmable Read-Only Memory
1.7 Field-Programmable Devices
1.8 Programmable Array Logic
1.9 Programmable Logic Array
1.10 Generic Array Logic Devices
1.11 Complex Programmable Array Logic
1.12 Field-Programmable Gate Array
1.12.1 Internal Architecture of Field-Programmable Gate Array
1.12.1.1 Configurable Logic Blocks
1.12.1.2 I/O Blocks
1.12.1.3 Programmable Interconnects
1.12.2 Design Flow of Field-Programmable Gate Array
1.12.3 Applications of Field-Programmable Gate Array in Medical Imaging
1.13 Summary
Bibliography
Chapter 2 Review of Digital Electronics Design
2.1 Introduction to Digital Design
2.1.1 Analog versus Digital Design
2.1.1.1 Analog Design
2.1.1.2 Digital Design
2.2 Number Systems
2.2.1 Binary
2.2.2 Octal and Hexadecimal
2.3 Logic Families
2.3.1 Digital Integrated Circuit Characteristics
2.3.2 Resistor–Transistor Logic
2.3.3 Diode–Transistor Logic
2.3.4 Emitter-Coupled Logic
2.3.5 Transistor–Transistor Logic
2.3.6 Complementary Metal Oxide Semiconductor Logic
2.4 Combinational Logic
2.4.1 Boolean Equation
2.4.2 Introduction to Combinational Logic Circuits
2.4.3 Analysis and Design Procedure
2.4.4 Adder and Subtractor
2.4.5 Decoder
2.4.6 Encoder
2.4.7 Multiplexer and Demultiplexer
2.5 Sequential Circuits
2.5.1 Introduction to Sequential Circuits
2.5.2 Steps Involved to Design a Sequential Circuit
2.5.3 Types of Sequential Logic Circuits
2.5.3.1 Comparison Table of Combinational and Sequential Logic Circuits
2.6 Storage Elements
2.6.1 SR Flip-Flop
2.6.2 D Flip-Flop
2.6.3 JK Flip-Flop
2.6.4 T Flip-Flop
2.7 Counters
2.7.1 Asynchronous Counters
2.7.2 Synchronous Counters
2.7.3 Registers
2.8 Memory
2.8.1 Read-Only Memory
2.8.2 Random Access Memory
2.8.3 Flash
2.8.4 Optical and Magnetic
References
Chapter 3 Verilog HDL for Digital and Analog Design
3.1 Introduction to Hardware Description Languages
3.2 Verilog for Digital Design
3.2.1 Verilog Language Basics
3.2.1.1 Keywords
3.2.1.2 Comment Line
3.2.1.3 Whitespaces
3.2.1.4 Identifier
3.2.1.5 Variables
3.2.1.6 Vector Data
3.2.1.7 Numbers or Constant Values
3.2.1.8 Parameter
3.2.1.9 Sequential Statements
3.2.2 Additional Constructs
3.2.2.1 Time Value (#)
3.2.2.2 @ (Sensitivity_List)
3.2.2.3 Generate
3.2.2.4 Gate Primitives
3.2.2.5 Tristate Gates
3.2.2.6 Switch-Level Primitives
3.2.3 Verilog Module Description
3.2.3.1 Ports
3.2.4 Operator Types
3.3 Modeling Types
3.3.1 Behavioral or Algorithmic Model
3.3.1.1 Blocking and Nonblocking Statements
3.3.2 Data flow or Register Transfer-Level Model
3.3.3 Gate-Level or Structural Model
3.3.4 Switch-Level Model
3.3.5 Mixed Model
3.4 User-Defined Primitives
3.5 Test Bench
3.6 Verilog for Analog Design
3.7 Verilog-A Basics
3.8 Summary
References
Chapter 4 Introduction to Hardware Description Languages
4.1 Introduction
4.1.1 Basic Principles of Hardware Description Languages
4.1.2 Basic Concepts of Hardware Description Languages
4.1.2.1 Timing and Concurrency
4.1.2.2 Hardware Simulation Process
4.1.3 Hardware Description Language Design Tool Suites
4.1.4 Types of Hardware Description Languages
4.1.5 Design Using Hardware Description Language
4.1.6 Hardware Description Languages for Digital Design
4.1.7 Very High-Scale Integrated Circuits Hardware Description Language
4.1.7.1 Entity Declaration
4.1.7.2 Architecture
4.1.8 Verilog
4.1.8.1 Lexical Tokens
4.1.8.2 Data Types
4.1.8.3 Timescale
4.1.8.4 Continuous Assignments
4.1.8.5 Procedural Assignment
4.1.8.6 Procedures: Always and Initial Blocks
4.1.9 Test Bench in Verilog
4.1.10 System Verilog
4.1.11 Test Bench Structure for System Verilog
4.1.11.1 Design under Test
4.1.11.2 Transaction
4.1.11.3 Interface
4.1.11.4 Generator
4.1.11.5 Driver
4.1.11.6 Monitor
4.1.11.7 Scoreboard
4.1.11.8 Test
4.1.11.9 Environment
4.1.11.10 Top
4.1.12 Verilog-AMS
4.1.13 Mini Project: Verilog and System Verilog
References
Chapter 5 Introduction to Hardware Description Languages (HDLs)
5.1 Introduction
5.1.1 Motivation
5.1.2 Structure of Hardware Description Language
5.1.3 History
5.1.4 Hardware Description Language and Programming Languages
5.1.5 Hardware Description Language Design Flow Expense
5.2 Design Simulation, Debugging, and Verification with Hardware Description Languages
5.3 Introduction to VHDL
5.3.1 Structure of Program
5.3.2 VHDL Variables
5.3.3 Functions, Libraries, and Packages
5.3.4 Design Elements
5.3.4.1 Structural
5.3.4.2 Dataflow
5.3.4.3 Behavioral
5.3.5 Writing a Simple Code with VHDL
5.3.6 Simulation and Synthesis
5.4 Introduction to Verilog
5.4.1 Structure of Program
5.4.2 Module Declarations
5.4.3 Verilog Variables, Operators, and Directives
5.4.3.1 Variable Data Types
5.4.3.2 Operators
5.4.4 Design Elements
5.4.4.1 Structural
5.4.4.2 Dataflow
5.4.4.3 Behavioral
5.4.4.4 Writing a Simple Code with Verilog
5.4.5 Simulation and Synthesis
References
Chapter 6 Emerging Trends in Nanoscale Semiconductor Devices
6.1 Introduction
6.2 Background
6.3 Nanotechnology Emerging Improvements
6.3.1 Technology Dependency (Bulk to Silicon-on-Insulator Technology)
6.3.2 Architectural Representation (Single- to MultiGate Field-Effect Transistor)
6.3.2.1 Double-Gate Silicon-on-Insulator Metal Oxide Semiconductor Field-Effect Transistors
6.3.2.2 Triple-Gate Silicon-on-Insulator Metal Oxide Semiconductor Field-Effect Transistors
6.3.2.3 Surrounding-Gate Silicon-on-Insulator Metal Oxide Semiconductor Field-Effect Transistors
6.3.2.4 Other Multigate Metal Oxide Semiconductor Field-Effect Transistors
6.3.3 Material Technology
6.3.3.1 Strained Silicon
6.3.3.2 High-k Gate Dielectric and Metal Gate Electrodes
6.3.4 Existing Metal Oxide Semiconductor Field-Effect Transistor Topologies at Nanoscale Regime
6.3.4.1 Junctionless Metal Oxide Semiconductor Field-Effect Transistor
6.3.4.2 Tunnel Field-Effect Transistor
6.3.4.3 Spintronics
6.3.4.4 Memristor
6.3.4.5 Graphene Transistors
6.3.4.6 High-Electron Mobility Transistor
6.4 Conclusions
References
Chapter 7 Design Challenges and Solutions in CMOS-Based FET
7.1 Introduction
7.2 Moore’s Law and the International Technology Roadmap for Semiconductors
7.3 CMOS Scaling Challenges and Solutions with New FET Geometries
7.4 NanoDevices Beyond Complementary Metal Oxide Semiconductor
7.5 Technical Challenges and Solutions
7.6 Conclusion
Acknowledgements
References
Chapter 8 Analytical Design of FET-Based Biosensors
8.1 Introduction
8.2 Types of Biosensors
8.2.1 Electrochemical Biosensor
8.2.2 Optical Biosensor
8.2.3 Piezoelectric Biosensor
8.2.4 Calorimetric Biosensor
8.3 Field-Effect Transistor–Based Biosensors
8.3.1 Working of Field-Effect Transistor–Based Biosensor
8.3.2 Some Common Types of Field-Effect Transistor–Based Biosensors
8.3.2.1 Ion-Sensitive Field-Effect Transistor Biosensor
8.3.2.2 Nanowire Field-Effect Transistor Biosensor
8.3.2.3 Carbon Nanotube Biosensor
8.3.2.4 Dielectrically Modulated Field-Effect Transistor Biosensor
8.3.2.5 Tunnel Field-Effect Transistor Biosensor
8.3.2.6 Junctionless Field-Effect Transistor Biosensor
8.4 Modeling of Field-Effect Transistor–Based Biosensors
8.4.1 Modeling of Dielectrically Modulated Field-Effect Transistor–Based Biosensors
8.4.1.1 Surface Potential
8.4.1.2 Electric Field
8.4.1.3 Threshold Voltage
8.4.1.4 Sensitivity
8.5 Summary
References
Chapter 9 Low-Power FET-Based Biosensors
9.1 Introduction
9.2 Principle of Operation
9.3 Silicon Nanowire Biosensor
9.4 Organic Field-Effect Transistor
9.5 Classification and Advances in Bio-FETs
9.6 ImmunoFET
9.7 Cell-Based Bio-FET
9.8 Conclusions
References
Chapter 10 Nanowire Array–Based Gate-All-Around MOSFET for Next-Generation Memory Devices
10.1 Introduction
10.2 Brief Review on Sentaurus TCAD
10.2.1 Sentaurus TCAD Codes
10.3 Device Design and Simulation
10.4 Results and Discussions
10.5 Conclusion
References
Chapter 11 Design of 7T SRAM Cell Using FinFET Technology
11.1 Introduction
11.2 SRAM Cell Architectures Based on CMOS Technology
11.2.1 6T SRAM Cell
11.2.2 7T SRAM Cell
11.2.3 8T SRAM Cell
11.2.4 10T SRAM Cell
11.2.5 12 T SRAM Cell
11.3 SRAM Cell Architectures Based on FinFET Technology
11.3.1 Proposed Design 7T SRAM Cell
11.3.2 Operations of 7T SRAM
11.4 Result Analysis
11.5 Different Types of Leakage Current in SRAM
11.5.1 Subthreshold Leakage Current
11.5.2 Gate Leakage
11.5.3 Junction Tunneling Leakage
11.5.4 Different Leakage Reduction Techniques
11.5.4.1 Self-controllable Voltage Level Technique
11.5.4.2 Lower Self-controllable Voltage Level
11.5.4.3 Upper Self-controllable Voltage Level
11.6 Conclusion
References
Chapter 12 Performance Analysis of AlGaN/GaN Heterostructure Field-Effect Transistor (HFET)
12.1 Introduction
12.2 Model Description
12.3 Results and Discussions
12.4 Conclusion
References
Chapter 13 Synthesis of Polymer-Based Composites for Application in Field-Effect Transistors
13.1 Introduction
13.2 Polymer-Based Composites
13.3 Methods of Synthesis
13.3.1 Solution Casting Method
13.3.2 Copolymerization
13.3.3 Addition of Ceramic Fillers
13.3.4 Sol–Gel process
13.3.5 Plasticization
13.3.6 Nanofillers
13.4 Conclusion
References
Chapter 14 Power Efficiency Analysis of Low-Power Circuit Design Techniques in 90-nm CMOS Technology
14.1 Introduction
14.2 Existing Low-Power Techniques
14.2.1 Conventional Complementary Metal Oxide Semiconductor
14.2.2 Pass-Transistor Logic Style
14.2.3 Differential Pass-Transistor Logic Style
14.2.4 Transmission Gate Logic Style
14.2.5 Gate Diffusion Input Logic Style
14.3 Proposed Low-Power Adiabatic Logic Techniques
14.3.1 Conventional Positive-Feedback Adiabatic Logic
14.3.2 Two-Phase Adiabatic Static Clocked Logic
14.4 Existing Design
14.4.1 4×1 Multiplexer Using Conventional Complementary Metal Oxide Semiconductor
14.4.2 4×1 Multiplexer Using Pass-Transistor Logic Style
14.4.3 4×1 Multiplexer Using Differential Pass-Transistor Logic Style
14.4.4 4×1 Multiplexer Using Transmission Gate Logic Style
14.4.5 4×1 Multiplexer Using Gate Diffusion Input Logic Style
14.5 Proposed Design
14.5.1 4×1 Multiplexer Using Conventional Positive-Feedback Adiabatic Logic
14.5.2 4×1 Multiplexer Using Two-Phase Adiabatic Static Clocked Logic
14.6 Comparative Analysis
14.7 Conclusion
References
Chapter 15 Macromodeling and Synthesis of Analog Circuits
15.1 Introduction
15.2 Parametric-Based Macromodeling
15.2.1 Symbolic Modeling
15.2.2 Posynomial Templates/Geometric Programming
15.2.3 Model Order Reduction
15.3 Nonparametric Macromodeling
15.3.1 Artificial Neural Network
15.3.2 Support Vector Machine
15.3.3 Extreme Learning Machine
15.4 Conclusions
References
Chapter 16 Performance-Linked Phase-Locked Loop Architectures: Recent Developments
16.1 Introduction
16.2 Performance-Linked Phase-Locked Loop Components
16.3 Recent Performance-Linked Architectures of Phase-Locked Loop Blocks
16.4 Design Challenges
16.5 Conclusion
References
Chapter 17 Review of Analog-to-Digital and Digital-to-Analog Converters for A Smart Antenna Application
17.1 Introduction
17.1.1 Butler Matrix
17.1.2 Architecture of Smart Antenna System
17.1.2.1 Receiver
17.1.2.2 Transmitter
17.2 Analog-to-Digital Converters and Digital-to-Analog Converters
17.2.1 Basics of Analog-to-Digital Conversion
17.2.2 Sampling
17.2.3 Quantization
17.2.4 Successive Approximation Register Analog-to-Digital Converter
17.2.4.1 Analog-to-Digital Converter
17.2.5 Flash Analog-to-Digital Converter
17.2.6 Pipelined Analog-to-Digital Converter
17.2.7 Delta–Sigma Analog-to-Digital Converter
17.3 Digital-to-Analog Converter
17.3.1 Feedback Digital-to-Analog Converter
17.3.2 Decimator
17.4 Conclusion
References
Chapter 18 Active Inductor–Based VCO for Wireless Communication
18.1 Introduction
18.1.1 Inductor–Capacitor Voltage-Controlled Oscillator
18.1.1.1 Linear Feedback Approach
18.1.1.2 Cross-Coupled Approach
18.2 Ring Voltage-Controlled Oscillator
18.3 Active Inductor
18.4 Voltage-Controlled Oscillator Using Active Inductor
18.5 Discrete Fourier Transform for Voltage-Controlled Oscillator
18.6 Summary
References
Chapter 19 Fault Simulation Algorithms: Verilog Implementation
19.1 Introduction
19.2 Logic Simulation
19.3 Fault Simulation
19.4 Verilog Coding for Simulation
References
Chapter 20 Hardware Protection through Logic Obfuscation
20.1 Introduction
20.2 Logic Working
20.3 Comparisons
20.4 Future Works
20.5 Conclusions
References
Index