Advanced VLSI design and testability issues

✍ Scribed by Mohapatra, Sushanta Kumar; Saxena, Sobhit; Tripathi, Suman Lata

• Publisher: CRC Press
• Year: 2020
• Tongue: English
• Leaves: 379
• Category: Library

✦ Synopsis

This bookfacilitates the VLSI-interestedindividuals with not only in-depth knowledge, but also the broad aspects of it by explaining its applications in different fields, includingimage processing and biomedical. The deep understanding of basic concepts gives you the power to develop a new application aspect, which is very well taken care of in this book by using simple language in explaining the concepts. In the VLSI world, the importance of hardware description languages cannot be ignored, as the designing of such dense and complex circuits is not possible without them. Both Verilog and VHDL languages are used here for designing. The current needs of high-performance integrated circuits (ICs) including low power devices and new emerging materials, which can play a very important role in achieving new functionalities, are the most interesting part of the book. The testing of VLSI circuits becomes more crucial than the designing of the circuits in this nanometer technology era. The role of fault simulation algorithms is very well explained, and its implementation using Verilog is the key aspect of this book. This book is well organized into 20 chapters. Chapter 1 emphasizes on uses of FPGA on various image processing and biomedical applications. Then, the descriptions enlighten the basic understanding of digital design from the perspective of HDL in Chapters 2-5. The performance enhancement with alternate material or geometry for silicon-based FET designs is focused in Chapters 6 and 7. Chapters 8 and 9 describe the study of bimolecular interactions with biosensing FETs. Chapters 10-13 deal with advanced FET structures available in various shapes, materials such as nanowire, HFET, and their comparison in terms of device performance metrics calculation. Chapters 14-18 describe different application-specific VLSI design techniques and challenges for analog and digital circuit designs. Chapter 19 explains the VLSI testability issues with the description of simulation and its categorization into logic and fault simulation for test pattern generation using Verilog HDL. Chapter 20 deals with a secured VLSI design with hardware obfuscation by hiding the IC's structure and function, which makes it much more difficult to reverse engineer.

✦ Table of Contents

Cover......Page 1
Half Title......Page 2
Title Page......Page 4
Copyright Page......Page 5
Table of Contents......Page 6
Preface to the First Edition......Page 10
Editors......Page 14
Contributors......Page 16
1.1 Introduction......Page 20
1.3 Read-Only Memory......Page 21
1.5 Erasable Programmable Read-Only Memory......Page 23
1.7 Field-Programmable Devices......Page 24
1.8 Programmable Array Logic......Page 25
1.9 Programmable Logic Array......Page 26
1.11 Complex Programmable Array Logic......Page 27
1.12.1.1 Configurable Logic Blocks......Page 29
1.12.2 Design Flow of Field-Programmable Gate Array......Page 31
1.13 Summary......Page 33
Bibliography......Page 34
Chapter 2 Review of Digital Electronics Design......Page 36
2.1.1.2 Digital Design......Page 37
2.3.1 Digital Integrated Circuit Characteristics......Page 38
2.3.4 Emitter-Coupled Logic......Page 39
2.4.1 Boolean Equation......Page 41
2.4.3 Analysis and Design Procedure......Page 43
2.4.4 Adder and Subtractor......Page 44
2.4.7 Multiplexer and Demultiplexer......Page 46
2.5.2 Steps Involved to Design a Sequential Circuit......Page 48
2.6 Storage Elements......Page 49
2.6.3 JK Flip-Flop......Page 50
2.6.4 T Flip-Flop......Page 51
2.7.1 Asynchronous Counters......Page 52
2.8 Memory......Page 53
2.8.1 Read-Only Memory......Page 54
2.8.4 Optical and Magnetic......Page 55
References......Page 56
Chapter 3 Verilog HDL for Digital and Analog Design......Page 58
3.1 Introduction to Hardware Description Languages......Page 59
3.2.1.2 Comment Line......Page 60
3.2.1.5 Variables......Page 61
3.2.1.6 Vector Data......Page 63
3.2.1.9 Sequential Statements......Page 64
3.2.2.2 @ (Sensitivity_List)......Page 68
3.2.2.5 Tristate Gates......Page 69
3.2.3 Verilog Module Description......Page 70
3.2.4 Operator Types......Page 71
3.3.1 Behavioral or Algorithmic Model......Page 73
3.3.1.1 Blocking and Nonblocking Statements......Page 74
3.3.2 Data flow or Register Transfer-Level Model......Page 75
3.3.3 Gate-Level or Structural Model......Page 76
3.3.4 Switch-Level Model......Page 77
3.4 User-Defined Primitives......Page 78
3.5 Test Bench......Page 79
3.6 Verilog for Analog Design......Page 81
3.7 Verilog-A Basics......Page 82
References......Page 85
Chapter 4 Introduction to Hardware Description Languages......Page 86
4.1.1 Basic Principles of Hardware Description Languages......Page 87
4.1.2.1 Timing and Concurrency......Page 88
4.1.4 Types of Hardware Description Languages......Page 89
4.1.7 Very High-Scale Integrated Circuits Hardware Description Language......Page 90
4.1.7.2 Architecture......Page 91
4.1.8.1 Lexical Tokens......Page 93
4.1.8.3 Timescale......Page 94
4.1.8.5 Procedural Assignment......Page 95
4.1.9 Test Bench in Verilog......Page 96
4.1.11 Test Bench Structure for System Verilog......Page 97
4.1.11.2 Transaction......Page 98
4.1.11.5 Driver......Page 99
4.1.11.7 Scoreboard......Page 100
4.1.11.9 Environment......Page 101
4.1.11.10 Top......Page 102
4.1.12 Verilog-AMS......Page 103
4.1.13 Mini Project: Verilog and System Verilog......Page 104
References......Page 110
Chapter 5 Introduction to Hardware Description Languages (HDLs)......Page 112
5.1.3 History......Page 113
5.1.4 Hardware Description Language and Programming Languages......Page 114
5.3 Introduction to VHDL......Page 115
5.3.1 Structure of Program......Page 116
5.3.3 Functions, Libraries, and Packages......Page 117
5.3.4.1 Structural......Page 118
5.3.4.2 Dataflow......Page 119
5.3.5 Writing a Simple Code with VHDL......Page 120
5.3.6 Simulation and Synthesis......Page 122
5.4.1 Structure of Program......Page 123
5.4.3.2 Operators......Page 124
5.4.4.1 Structural......Page 125
5.4.4.3 Behavioral......Page 126
5.4.4.4 Writing a Simple Code with Verilog......Page 127
References......Page 128
Chapter 6 Emerging Trends in Nanoscale Semiconductor Devices......Page 130
6.2 Background......Page 131
6.3.1 Technology Dependency (Bulk to Silicon-on-Insulator Technology)......Page 134
6.3.2 Architectural Representation (Single- to MultiGate Field-Effect Transistor)......Page 135
6.3.2.1 Double-Gate Silicon-on-Insulator Metal Oxide Semiconductor Field-Effect Transistors......Page 136
6.3.3 Material Technology......Page 137
6.3.4.1 Junctionless Metal Oxide Semiconductor Field-Effect Transistor......Page 138
6.3.4.3 Spintronics......Page 140
6.3.4.4 Memristor......Page 141
6.3.4.6 High-Electron Mobility Transistor......Page 142
6.4 Conclusions......Page 143
References......Page 144
7.2 Moore’s Law and the International Technology Roadmap for Semiconductors......Page 148
7.3 CMOS Scaling Challenges and Solutions with New FET Geometries......Page 151
7.4 NanoDevices Beyond Complementary Metal Oxide Semiconductor......Page 155
7.5 Technical Challenges and Solutions......Page 161
References......Page 163
8.1 Introduction......Page 166
8.2.1 Electrochemical Biosensor......Page 168
8.3 Field-Effect Transistor–Based Biosensors......Page 169
8.3.1 Working of Field-Effect Transistor–Based Biosensor......Page 170
8.3.2.1 Ion-Sensitive Field-Effect Transistor Biosensor......Page 171
8.3.2.3 Carbon Nanotube Biosensor......Page 172
8.3.2.4 Dielectrically Modulated Field-Effect Transistor Biosensor......Page 173
8.3.2.6 Junctionless Field-Effect Transistor Biosensor......Page 174
8.4 Modeling of Field-Effect Transistor–Based Biosensors......Page 175
8.4.1.1 Surface Potential......Page 177
8.4.1.2 Electric Field......Page 179
8.4.1.3 Threshold Voltage......Page 181
8.4.1.4 Sensitivity......Page 182
References......Page 184
9.1 Introduction......Page 188
9.2 Principle of Operation......Page 189
9.3 Silicon Nanowire Biosensor......Page 192
9.4 Organic Field-Effect Transistor......Page 193
9.5 Classification and Advances in Bio-FETs......Page 195
9.6 ImmunoFET......Page 198
9.7 Cell-Based Bio-FET......Page 199
9.8 Conclusions......Page 202
References......Page 203
10.1 Introduction......Page 208
10.2 Brief Review on Sentaurus TCAD......Page 212
10.2.1 Sentaurus TCAD Codes......Page 213
10.4 Results and Discussions......Page 214
References......Page 219
11.1 Introduction......Page 222
11.2.1 6T SRAM Cell......Page 223
11.2.3 8T SRAM Cell......Page 224
11.3 SRAM Cell Architectures Based on FinFET Technology......Page 225
11.3.1 Proposed Design 7T SRAM Cell......Page 226
11.3.2 Operations of 7T SRAM......Page 227
11.4 Result Analysis......Page 228
11.5.2 Gate Leakage......Page 229
11.5.4.3 Upper Self-controllable Voltage Level......Page 230
References......Page 232
12.1 Introduction......Page 234
12.3 Results and Discussions......Page 235
References......Page 240
13.1 Introduction......Page 244
13.2 Polymer-Based Composites......Page 245
13.3.3 Addition of Ceramic Fillers......Page 247
13.3.5 Plasticization......Page 248
13.4 Conclusion......Page 249
References......Page 250
Chapter 14 Power Efficiency Analysis of Low-Power Circuit Design Techniques in 90-nm CMOS Technology......Page 252
14.1 Introduction......Page 253
14.2.1 Conventional Complementary Metal Oxide Semiconductor......Page 254
14.2.2 Pass-Transistor Logic Style......Page 255
14.2.4 Transmission Gate Logic Style......Page 256
14.2.5 Gate Diffusion Input Logic Style......Page 257
14.3 Proposed Low-Power Adiabatic Logic Techniques......Page 258
14.3.1 Conventional Positive-Feedback Adiabatic Logic......Page 259
14.4.2 4×1 Multiplexer Using Pass-Transistor Logic Style......Page 260
14.4.5 4×1 Multiplexer Using Gate Diffusion Input Logic Style......Page 261
14.5.1 4×1 Multiplexer Using Conventional Positive-Feedback Adiabatic Logic......Page 262
14.6 Comparative Analysis......Page 264
14.7 Conclusion......Page 266
References......Page 267
15.1 Introduction......Page 270
15.2 Parametric-Based Macromodeling......Page 271
15.2.1 Symbolic Modeling......Page 272
15.2.3 Model Order Reduction......Page 275
15.3.1 Artificial Neural Network......Page 278
15.3.2 Support Vector Machine......Page 280
15.3.3 Extreme Learning Machine......Page 281
References......Page 283
16.1 Introduction......Page 290
16.2 Performance-Linked Phase-Locked Loop Components......Page 291
16.3 Recent Performance-Linked Architectures of Phase-Locked Loop Blocks......Page 293
16.4 Design Challenges......Page 303
References......Page 304
17.1 Introduction......Page 310
17.1.2.1 Receiver......Page 313
17.1.2.2 Transmitter......Page 315
17.2.1 Basics of Analog-to-Digital Conversion......Page 316
17.2.2 Sampling......Page 317
17.2.3 Quantization......Page 318
17.2.4 Successive Approximation Register Analog-to-Digital Converter......Page 319
17.2.4.1 Analog-to-Digital Converter......Page 320
17.2.5 Flash Analog-to-Digital Converter......Page 322
17.2.6 Pipelined Analog-to-Digital Converter......Page 323
17.3.2 Decimator......Page 324
17.4 Conclusion......Page 325
References......Page 326
18.1 Introduction......Page 330
18.1.1.1 Linear Feedback Approach......Page 331
18.1.1.2 Cross-Coupled Approach......Page 332
18.3 Active Inductor......Page 333
18.4 Voltage-Controlled Oscillator Using Active Inductor......Page 334
18.5 Discrete Fourier Transform for Voltage-Controlled Oscillator......Page 338
18.6 Summary......Page 339
References......Page 341
19.2 Logic Simulation......Page 344
19.3 Fault Simulation......Page 346
19.4 Verilog Coding for Simulation......Page 349
References......Page 357
20.1 Introduction......Page 358
20.2 Logic Working......Page 360
20.3 Comparisons......Page 364
20.4 Future Works......Page 365
References......Page 366
Index......Page 370

✦ Subjects

Integrated circuits--Very large scale integration--Design and construction;TECHNOLOGY / Electricity;TECHNOLOGY / Electronics / Circuits / General;Electronic books;Integrated circuits -- Very large scale integration -- Design and construction