This paper presents a transistor optimization methodology for low-power analog integrated CMOS circuits, relying on the physics-based gm/ID characteristics as a design optimization guide. Our custom layout tool LIT implements and uses the ACM MOS compact model in the optimization loop. The methodolo
β¦ LIBER β¦
[ACM Press the 19th annual symposium - Ouro Preto, MG, Brazil (2006.08.28-2006.09.01)] Proceedings of the 19th annual symposium on Integrated circuits and systems design - SBCCI '06 - Power constrained design optimization of analog circuits based on physical gm/ID characteristics
β Scribed by Girardi, Alessandro; Bampi, Sergio
- Book ID
- 121530454
- Publisher
- ACM Press
- Year
- 2006
- Tongue
- English
- Weight
- 476 KB
- Category
- Article
- ISBN-13
- 9781595934796
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