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A synthesis for testability scheme for finite state machines using clock control

✍ Scribed by Einspahr, K.L.; Mehta, S.K.; Seth, S.C.

Book ID: 119778569
Publisher: IEEE
Year: 1999
Tongue: English
Weight: 387 KB
Volume: 18
Category: Article
ISSN: 0278-0070
DOI: 10.1109/43.811327

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