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A Scan-BIST Structure to Test Delay Faults in Sequential Circuits

โœ Scribed by P. Girard; C. Landrault; V. Moreda; S. Pravossoudovitch; A. Virazel


Book ID
110261620
Publisher
Springer US
Year
1999
Tongue
English
Weight
114 KB
Volume
14
Category
Article
ISSN
0923-8174

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We propose a testability enhancement technique for delay faults in standard scan circuits that does not involve modiยฎcations to the scan chain. Extra logic is placed on next-state variables, and if necessary, on primary inputs, and can be resynthesized with the circuit to minimize its hardware and p