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A note on designing two-level carry-skip adders

โœ Scribed by Chan, Pak K. ;Schlag, Martine D. F.


Book ID
105011560
Publisher
Springer
Year
1991
Tongue
English
Weight
573 KB
Volume
3
Category
Article
ISSN
0922-5773

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Performance analysis of a two-level carr
โœ Antonio G.M. Strollo; Ettore Napoli ๐Ÿ“‚ Article ๐Ÿ“… 1998 ๐Ÿ› Elsevier Science ๐ŸŒ English โš– 478 KB

Performance evaluation of a two-level carry-skip adder using complementary pass-transistor logic (CPL) is presented in this paper. The adder is compared with a fulI-CMOS version of the two-level carry-skip architecture, with a carry-lookahead adder automatically generated with ALLIANCE CAD tools and