In designing a digital circuit with a microprocessor, there are several simulation levels. Using a logic synthesis tool and a layout synthesis tool, a lower-level simulation model can be generated from a design RT level described in HDLs. There is trade-off between accuracy and speed of simulations.
β¦ LIBER β¦
A model for the high-level description and simulation of VLSI networks
β Scribed by van der Hoeven, A.J.; de Lange, A.A.J.; Deprettere, E.F.; Dewilde, P.M.
- Book ID
- 117878326
- Publisher
- IEEE
- Year
- 1990
- Tongue
- English
- Weight
- 596 KB
- Volume
- 10
- Category
- Article
- ISSN
- 0272-1732
- DOI
- 10.1109/40.57730
No coin nor oath required. For personal study only.
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