✦ LIBER ✦
Automatic generation of command level simulation model of a processor from rt level description
✍ Scribed by Hiroki Akaboshi; Hiroto Yasuura
- Publisher
- John Wiley and Sons
- Year
- 1996
- Tongue
- English
- Weight
- 684 KB
- Volume
- 79
- Category
- Article
- ISSN
- 1042-0967
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✦ Synopsis
In designing a digital circuit with a microprocessor, there are several simulation levels. Using a logic synthesis tool and a layout synthesis tool, a lower-level simulation model can be generated from a design RT level described in HDLs. There is trade-off between accuracy and speed of simulations. A lower-level simulation model can simulate more accurately. There is little support for generating high-level simulation models in which a human designer is required. In this paper, m algorithm is proposed for high-level simulption model generation and experimental results are shown.