✦ LIBER ✦
Compiling gate RC models into a top level simulation model for rough timing analysis of VLSI circuits
✍ Scribed by Zainalabedin Navabi
- Publisher
- Elsevier Science
- Year
- 1991
- Tongue
- English
- Weight
- 723 KB
- Volume
- 15
- Category
- Article
- ISSN
- 0141-9331
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