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A Mapping Flow for Dynamically Reconfigurable Multi-Core System-on-Chip Design

โœ Scribed by Beretta, I.; Rana, V.; Atienza, D.; Sciuto, D.


Book ID
117908562
Publisher
IEEE
Year
2011
Tongue
English
Weight
709 KB
Volume
30
Category
Article
ISSN
0278-0070

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A restructurable (reconfigurable) parallel VLSI processor designed to minimize the operation delay time which can be generally used for various operations necessary for controlling an intelligent robot was proposed previously by the authors. This processor is constructed by connecting a number of pr