high-performance parallel and pipelined architecture (MViP) has been proposed for MPEG-2 coding. A macrocell for use in an ASIC has been designed and implemented using ES2 0.7 Am dual-layer-metal CMOS technology. This macrocell consists of about 120,000 equivalent gates and is able to execute, in re
A high-level datapath synthesis method for pipelined structures
✍ Scribed by Péter Arató; lstván Béres; Andrzej Rucinski; Robert Davis; Roy Torbert
- Publisher
- Elsevier Science
- Year
- 1994
- Tongue
- English
- Weight
- 696 KB
- Volume
- 25
- Category
- Article
- ISSN
- 0026-2692
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