A High-Performance Architecture with a Macroblock-Level-Pipeline for MPEG-2 Coding

✍ Scribed by José M. Fernández; Félix Moreno; Juan M. Meneses

• Publisher: Elsevier Science
• Year: 1996
• Tongue: English
• Weight: 90 KB
• Volume: 2
• Category: Article
• ISSN: 1077-2014
• DOI: 10.1006/rtim.1996.0034

✦ Synopsis

high-performance parallel and pipelined architecture (MViP) has been proposed for MPEG-2 coding. A macrocell for use in an ASIC has been designed and implemented using ES2 0.7 Am dual-layer-metal CMOS technology. This macrocell consists of about 120,000 equivalent gates and is able to execute, in real time, the Loop of an MPEG-2 coder for main profile/main level (MP@ML) resolution when running at 40 MHz. MViP is made up of several specific-purpose units (SPUs), an RISC core processor, banks of internal memory and an optimized crossbar network which lets these pipelined SPUs and RISC core work in parallel at a macroblock-level-pipeline, greatly increasing silicon efficiency.