A data optimization test technique for characterizing embedded ADCs

✍ Scribed by J. Raczkowycz; S. Allott; T. I. Pritchard

• Publisher: Springer US
• Year: 1996
• Tongue: English
• Weight: 550 KB
• Volume: 9
• Category: Article
• ISSN: 0923-8174
• DOI: 10.1007/bf00137572

✦ Synopsis

A novel data optimization test technique is presented which utilizes a BIST structure, an ADC model and histogram data to characterize embedded ADCs. A practical 8 bit ADC is modeled and then characterized using 20% less data points then conventional analysis with a 78% reduction in the amount of data required to be shifted off-chip. Comparisons between theoretical, modeled and practical results are also made in the paper.