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A 9-bit 80 MS/s Successive Approximation Register Analog-to-Digital Converter With a Capacitor Reduction Technique

✍ Scribed by Young-Kyun Cho, ;Young-Deuk Jeon, ;Jae-Won Nam, ;Jong-Kee Kwon,

Book ID: 120522745
Publisher: Institute of Electrical and Electronics Engineers
Year: 2010
Tongue: English
Weight: 804 KB
Volume: 57
Category: Article
ISSN: 1549-7747
DOI: 10.1109/TCSII.2010.2048387

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