A 60-GHz LNA with 18.6-dB gain and 5.7-dB NF in 90-nm CMOS
✍ Scribed by Kai Kang; James Brinkhoff; Fujiang Lin
- Book ID
- 102522054
- Publisher
- John Wiley and Sons
- Year
- 2010
- Tongue
- English
- Weight
- 198 KB
- Volume
- 52
- Category
- Article
- ISSN
- 0895-2477
No coin nor oath required. For personal study only.
✦ Synopsis
Abstract
A 60‐GHz low‐noise amplifier (LNA) is implemented in a commercial 90‐nm RF CMOS process. A scalable model based on electromagnetic simulation is adopted to model on‐chip microstrip transmission lines. First‐pass silicon success has been achieved by accurate modeling of passive and active devices and careful layout. The three‐stage LNA achieves 18.6‐dB gain, a noise figure of 5.7 dB, and an input P~1dB~ of −14.8 dBm. It consumes 24 mA from a 1.2‐V supply. The total LNA die area with pads is 1.4 × 0.5 mm^2^. © 2010 Wiley Periodicals, Inc. Microwave Opt Technol Lett 52: 2056–2059, 2010; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.25379
📜 SIMILAR VOLUMES
## Abstract A 30‐GHz (Ka‐band) low‐noise amplifier (LNA) with 10 mW power consumption (P~DC~) using standard 0.18‐μm CMOS technology was designed and implemented. To achieve sufficient gain, this LNA was composed of three cascade common‐source stages, and a series peaking inductor (L~g3~) was added
## Abstract A high‐gain and low‐noise CMOS distributed amplifier (DA) is proposed.Flat and high S~21~ and flat and low NF was achieved simultaneously by using the proposed dual‐inductive‐peaking (L~D~ and L~P~) cascade gain cell, which constituted a cascode‐stage with a low‐Q RLC load and two induc