✦ LIBER ✦

A 20-ns 256 K×4 FIFO memory

✍ Scribed by Hashimoto, M.; Nomura, M.; Sasaki, K.; Komatsuzaki, K.; Fujiwara, H.; Honzawa, T.; Abe, K.; Tachibana, T.; Kitagawa, N.

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

8-ns CMOS 64 K×4 and 256 K×1 SRAMs

✍ Flannagan, S.T.; Pelley, P.H.; Herr, N.; Engles, B.E.; Feng, T.; Nogle, S.G.; Ea 📂 Article 📅 1990 🏛 IEEE 🌐 English ⚖ 780 KB

25-ns 256K×1/64K×4 CMOS SRAM's

✍ Kayano, S.; Ichinose, K.; Kohno, Y.; Shinohara, H.; Anami, K.; Murakami, S.; Wad 📂 Article 📅 1986 🏛 IEEE 🌐 English ⚖ 883 KB

A 14 ns 256 K×1 CMOS SRAM with multiple

✍ Voss, P.H.; Pfennings, L.C.M.G.; Phelan, C.G.; O'Connell, C.M.; Davies, T.J.; On 📂 Article 📅 1989 🏛 IEEE 🌐 English ⚖ 634 KB

A 50-ns CMOS 256 K EEPROM

✍ Ting, T.-K.J.; Chang, T.; Lin, T.; Jenq, C.S.; Naiff, K.L.C. 📂 Article 📅 1988 🏛 IEEE 🌐 English ⚖ 621 KB

A 6-ns cycle 256-kb cache memory and mem

✍ Heald, R.A.; Holst, J.C. 📂 Article 📅 1993 🏛 IEEE 🌐 English ⚖ 546 KB

A 50-ns 256 K CMOS split-gate EPROM

✍ Ali, S.B.; Sani, B.; Shubat, A.S.; Sinai, K.; Kazerounian, R.; Hu, C.-J.; Ma, Y. 📂 Article 📅 1988 🏛 IEEE 🌐 English ⚖ 700 KB