✦ LIBER ✦

A 14-ns 1-Mbit CMOS SRAM with variable bit organization

✍ Scribed by Kohno, Y.; Wada, T.; Anami, K.; Kawai, Y.; Yuzuriha, K.; Matsukawa, T.; Kayano, S.

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

A 46-ns 1-Mbit CMOS SRAM

✍ Shimada, H.; Kawashima, S.; Itoh, H.; Suzuki, N.; Yabu, T. 📂 Article 📅 1988 🏛 IEEE 🌐 English ⚖ 571 KB

A 9-ns 1-Mbit CMOS SRAM

✍ Sasaki, K.; Ishibashi, K.; Yamanaka, T.; Hashimoto, N.; Nishida, T.; Shimohigash 📂 Article 📅 1989 🏛 IEEE 🌐 English ⚖ 955 KB

A 15-ns 1-Mbit CMOS SRAM

✍ Sasaki, K.; Hanamura, S.; Ueda, K.; Oono, T.; Minato, O.; Sakai, Y.; Meguro, S.; 📂 Article 📅 1988 🏛 IEEE 🌐 English ⚖ 609 KB

A 25-ns 4-Mbit CMOS SRAM with dynamic bi

✍ Miyaji, F.; Matsuyama, Y.; Kanaishi, Y.; Senoh, K.; Emori, T.; Hagiwara, Y. 📂 Article 📅 1989 🏛 IEEE 🌐 English ⚖ 747 KB

A 34-ns 1-Mbit CMOS SRAM using triple po

✍ Wada, T.; Hirose, T.; Shinohara, H.; Kawai, Y.; Yuzuriha, K.; Kohno, Y.; Kayano, 📂 Article 📅 1987 🏛 IEEE 🌐 English ⚖ 945 KB

A 25-ns low-power full-CMOS 1-Mbit (128

✍ Chu, S.T.; Dikken, J.; Hartgring, C.D.; List, F.J.; Raemaekers, J.G.; Bells, S.A 📂 Article 📅 1988 🏛 IEEE 🌐 English ⚖ 678 KB