5.5 GHz 802.11a 0.18 μm CMOS pre-power amplifier core with on-chip linearisation
✍ Scribed by Toner, B.; Dharmalinggam, R.; Fusco, V.F.
- Book ID
- 114455320
- Publisher
- The Institution of Electrical Engineers
- Year
- 2004
- Tongue
- English
- Weight
- 275 KB
- Volume
- 151
- Category
- Article
- ISSN
- 1350-2417
No coin nor oath required. For personal study only.
📜 SIMILAR VOLUMES
## Abstract This paper presents a low‐noise amplifier (LNA) design which includes image rejection and gain control. The proposed LNA adopts a cascode topology with a notch filter combined with a gain control function. The performance of the proposed LNA is compared with conventional cascode topolog
## Abstract A 30‐GHz (Ka‐band) low‐noise amplifier (LNA) with 10 mW power consumption (P~DC~) using standard 0.18‐μm CMOS technology was designed and implemented. To achieve sufficient gain, this LNA was composed of three cascade common‐source stages, and a series peaking inductor (L~g3~) was added