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A 4.5 mW 3-5 GHz low-noise amplifier in 0.25-μm silicon-on-insulator CMOS process for power-constraint application

✍ Scribed by Iji, A.; Zhu, X.; Heimlich, M.

Book ID
118764622
Publisher
John Wiley and Sons
Year
2012
Tongue
English
Weight
585 KB
Volume
55
Category
Article
ISSN
0895-2477

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## Abstract A concurrent 2.4/5.2‐GHz dual‐band monolithic low‐noise amplifier implemented with a 0.18‐μm mixed‐signal CMOS technology is reported for the first time. This LNA only consumed 3‐mW power, and achieved minimum noise figures of 3.3 and 3.26 dB and 2.4 and 5.2 GHz, respectively. Input and