๐”– Bobbio Scriptorium
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Yield-enhancement of a large systolic array chip

โœ Scribed by W.R. Moore; M.J. Day


Publisher
Elsevier Science
Year
1984
Tongue
English
Weight
496 KB
Volume
24
Category
Article
ISSN
0026-2714

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A Reconfigurable Bit-Serial VLSI Systoli
โœ Paul J. Murtagh; Ah Chung Tsoi ๐Ÿ“‚ Article ๐Ÿ“… 1997 ๐Ÿ› Elsevier Science ๐ŸŒ English โš– 687 KB

A dynamically reconfigurable bit-serial systolic array implemented in 1.2-ยตm double-metal P-well CMOS is described. This processor array is proposed as the central computational unit in the Reconfigurable Systolic Array (RSA) neuro-computer and performance estimates suggest that a 64 IC system (cont