A Reconfigurable Bit-Serial VLSI Systolic Array Neuro-Chip

✍ Scribed by Paul J. Murtagh; Ah Chung Tsoi

• Publisher: Elsevier Science
• Year: 1997
• Tongue: English
• Weight: 687 KB
• Volume: 44
• Category: Article
• ISSN: 0743-7315
• DOI: 10.1006/jpdc.1997.1343

✦ Synopsis

A dynamically reconfigurable bit-serial systolic array implemented in 1.2-µm double-metal P-well CMOS is described. This processor array is proposed as the central computational unit in the Reconfigurable Systolic Array (RSA) neuro-computer and performance estimates suggest that a 64 IC system (containing a total of 1024 usable processors) can achieve a learning rate of 1134 MCUPS on the NETtalk problem. The architecture employs reconfiguration techniques for both fault-tolerance and functionality, and allows a number of neural network models (in both the recall and learning phases) from associative memory networks, supervised networks, and unsupervised networks to be supported.