VLSI Circuits and Embedded Systems

✍ Scribed by Hafiz Md. Hasan Babu

• Publisher: CRC Press
• Year: 2022
• Tongue: English
• Leaves: 510
• Edition: 1
• Category: Library

✦ Synopsis

Very Large-Scale Integration (VLSI) creates an integrated circuit (IC) by combining thousands of transistors into a single chip. While designing a circuit, reduction of power consumption is a great challenge. VLSI designs reduce the size of circuits which eventually reduces the power consumption of the devices. However, it increases the complexity of the digital system. Therefore, computer-aided design tools are introduced into hardware design processes.

Unlike the general-purpose computer, an embedded system is engineered to manage a wide range of processing tasks. Single or multiple processing cores manage embedded systems in the form of microcontrollers, digital signal processors, field-programmable gate arrays, and application-specific integrated circuits. Security threats have become a significant issue since most embedded systems lack security even more than personal computers. Many embedded systems hacking tools are readily available on the internet. Hacking in the PDAs and modems is a pervasive example of embedded systems hacking.

This book explores the designs of VLSI circuits and embedded systems. These two vast topics are divided into four parts. In the book's first part, the Decision Diagrams (DD) have been covered. DDs have extensively used Computer-Aided Design (CAD) software to synthesize circuits and formal verification. The book's second part mainly covers the design architectures of Multiple-Valued Logic (MVL) Circuits. MVL circuits offer several potential opportunities to improve present VLSI circuit designs. The book's third part deals with Programmable Logic Devices (PLD). PLDs can be programmed to incorporate a complex logic function within a single IC for VLSI circuits and Embedded Systems. The fourth part of the book concentrates on the design architectures of Complex Digital Circuits of Embedded Systems. As a whole, from this book, core researchers, academicians, and students will get the complete picture of VLSI Circuits and Embedded Systems and their applications.

✦ Table of Contents

Cover
Half Title
Title Page
Copyright Page
Dedication
Contents
List of Figures
List of Tables
Preface
Author Bio
Acknowledgments
Acronyms
Introduction
SECTION I: An Overview About Decision Diagrams
Part 1
CHAPTER 1: Shared Multi-Terminal Binary Decision Diagrams
1.1. INTRODUCTION
1.2. PRELIMINARIES
1.2.1. Shared Multi-Terminal Binary Decision Diagrams
1.3. AN OPTIMIZATION ALGORITHM FOR SMTBDD(K)S
1.3.1. The Weight Calculation Procedure
1.3.2. Optimization of SMTBDD(3)s
1.4. SUMMARY
CHAPTER 2: Multiple-Output Functions
2.1. INTRODUCTION
2.1.1. Basic Definitions
2.2. BINARY DECISION DIAGRAMS FOR MULTIPLE-OUTPUT FUNCTIONS
2.2.1. SBDDs and MTBDDs
2.2.2. BDDs for CFs
2.2.2.1. BDDs for CFs of Multiple-Output Functions
2.2.3. Comparison of Various BDDs
2.3. CONSTRUCTION OF COMPACT BDDS FOR CFS
2.3.1. Formulation of the Problem
2.3.2. Ordering of Output Variables
2.3.3. Interleaving-Based Sampling Schemes for Ordering of Input Variables
2.3.3.1. Generating Samples from Output Functions
2.3.3.2. Interleaving the Variable Orderings of Samples
2.3.4. Interleaving Method for Input Variables and Output Variables
2.3.5. Algorithm for Ordering the Variables
2.4. SUMMARY
CHAPTER 3: Shared Multiple-Valued DDs for Multiple-Output Functions
3.1. INTRODUCTION
3.2. DECISION DIAGRAMS
3.2.1. Binary Decision Diagrams
3.2.2. Multiple-Valued Decision Diagrams
3.2.2.1. Shared Multiple-Valued Decision Diagrams
3.3. CONSTRUCTION OF COMPACT SMDDS
3.3.1. Pairing of Binary Input Variables
3.3.1.1. The Method
3.3.2. Ordering of Input Variables
3.4. SUMMARY
CHAPTER 4: Heuristics to Minimize Multiple-Valued Decision Diagrams
4.1. INTRODUCTION
4.2. BASIC PROPERTIES
4.3. MULTIPLE-VALUED DECISION DIAGRAMS
4.3.1. Size of MDDs
4.4. MINIMIZATION OF MDDS
4.4.1. Pairing of 2-Valued Inputs
4.4.2. Ordering of Multiple-Valued Variables
4.5. SUMMARY
CHAPTER 5: TDM Realizations of Multiple-Output Functions
5.1. INTRODUCTION
5.2. DECISION DIAGRAMS FOR MULTIPLE-OUTPUT FUNCTIONS
5.2.1. Shared Binary Decision Diagrams
5.2.2. Shared Multiple-Valued Decision Diagrams
5.2.3. Shared Multi-Terminal Multiple-Valued Decision Diagrams
5.3. TDM REALIZATIONS
5.3.1. TDM Realizations Based on SBDDs
5.3.2. TDM Realizations Based on SMDDs
5.3.3. TDM Realizations Based on SMTMDDs
5.3.4. Comparison of TDM Realizations
5.4. REDUCTION OF SMTMDDS
5.5. UPPER BOUNDS ON THE SIZEN OF DDS
5.6. SUMMARY
CHAPTER 6: Multiple-Output Switching Functions
6.1. INTRODUCTION
6.2. DEFINITIONS AND BASIC PROPERTIES
6.3. DECISION DIAGRAMS
6.3.1. 2-Valued Pseudo-Kronecker Decision Diagrams
6.3.2. Multiple-Valued Pseudo-Kronecker Decision Diagrams
6.4. OPTIMIZATION OF 4-VALUED PKDDS
6.4.1. Pairing of 2-Valued Input Variables
6.4.2. Ordering of 4-Valued Variables
6.4.3. Selection of Expansions
6.5. SUMMARY
SECTION II: An Overview About Design Architectures of Multiple-Valued Circuits
Part 2
CHAPTER 7: Multiple-Valued Flip-Flops Using Pass Transistor Logic
7.1. INTRODUCTION
7.1.1. Realization of Multiple Valued Flip-Flops Using Pass Transistor Logic
7.1.2. Implementation of MVFF with Binary Coding and Decoding Using PTL
7.2. MVFF WITHOUT BINARY ENCODING OR DECODING
7.2.1. Properties of Pass Transistor and a Threshold Gate
7.2.2. Realization of Multiple-Valued Inverter Using Threshold Gates
7.2.3. Realization MVFF Using Multiple-Valued Pass Transistor Logic
7.3. SUMMARY
CHAPTER 8: Voltage-Mode Pass Transistor-Based Multi-Valued Multiple-Output Logic Circuits
8.1. INTRODUCTION
8.2. BASIC DEFINITIONS AND TERMINOLOGIES
8.3. THE METHOD
8.3.1. Conversion of Binary Logic Functions into MVL Functions
8.3.2. Pairing of the Functions
8.3.3. Output Stage
8.3.4. Basic Circuit Structure and Operation
8.3.4.1. Literal Generation
8.4. SUMMARY
CHAPTER 9: Multiple-Valued Input Binary-Valued Output Functions
9.1. INTRODUCTION
9.2. BASIC DEFINITIONS
9.3. TRANSFORMATION OF TWO-VALUED VARIABLES INTO MULTIPLE-VALUED VARIABLES
9.3.1. Algorithms for Minimizing the Multiple-Valued Functions
9.4. SUMMARY
CHAPTER 10: Digital Fuzzy Operations Using Multi-Valued Fredkin Gates
10.1. INTRODUCTION
10.2. REVERSIBLE LOGIC
10.2.1. Some Basic Reversible Gates and Classical Digital Logic Using these Gates
10.2.2. Multi-Valued Fredkin Gate
10.3. FUZZY SETS AND RELATION
10.4. THE CIRCUIT
10.4.1. Fuzzy Operations Using MVFG
10.4.2. Systolic Array Structure for Composition of Fuzzy Relations
10.5. SUMMARY
CHAPTER 11: Multiple-Valued Multiple-Output Logic Expressions Using LUT
11.1. INTRODUCTION
11.2. BASIC DEFINITIONS AND PROPERTIES
11.2.1. Product Terms
11.2.1.1. Prime Implicants
11.2.2. Minimal SOPs
11.2.3. MVSOP Expressions Using KC
11.3. THE METHOD
11.3.1. Support Set Matrix
11.3.2. Pair Support Matrix
11.4. THE ALGORITHM FOR MINIMIZATION OF MVMOFS USING KC
11.5. REALIZATION OF MVMOFS USING CURRENT MODE CMOS
11.6. SUMMARY
SECTION III: An Overview About Programmable Logic Devices
Part 3
CHAPTER 12: LUT-Based Matrix Multiplication Using Neural Networks
12.1. INTRODUCTION
12.2. BASIC DEFINITIONS
12.3. THE METHOD
12.4. SUMMARY
CHAPTER 13: Easily Testable PLAs Using Pass Transistor Logic
13.1. INTRODUCTION
13.2. PRODUCT LINE GROUPING
13.3. THE DESIGN
13.4. THE TECHNIQUE FOR PRODUCT LINE GROUPING
13.5. SUMMARY
CHAPTER 14: Genetic Algorithm for Input Assignment for Decoded-PLAs
14.1. INTRODUCTION TO DECODERS
14.1.1. Decoders as Product Generators
14.2. DECODED PLA
14.2.1. Advantages
14.3. BASIC DEFINITIONS
14.4. GENETIC ALGORITHM
14.4.1. GA Terminology
14.4.2. The Simple GA
14.4.3. The Steady-State Genetic Algorithm
14.5. GENETIC OPERATORS
14.5.1. Selection
14.6. CROSSOVER
14.6.1. Mutation
14.6.2. Inversion
14.7. GA FOR DECODED-PLAS
14.7.1. Problem Encoding
14.7.2. Fitness Function
14.7.3. Developed GA
14.7.4. Decoded AND-EXOR PLA Implementation
14.8. SUMMARY
CHAPTER 15: FPGA-Based Multiplier Using LUT Merging Theorem
15.1. INTRODUCTION
15.2. LUT MERGING THEOREM
15.3. THE MULTIPLIER CIRCUIT USING THE LUT MERGING THEOREM
15.4. SUMMARY
CHAPTER 16: Look-Up Table-Based Binary Coded Decimal Adder
16.1. INTRODUCTION
16.2. THE DESIGN OF LUT-BASED BCD ADDER
16.2.1. Parallel BCD Addition Method
16.2.2. Parallel BCD Adder Circuit Using LUT
16.3. SUMMARY
CHAPTER 17: Place and Route Algorithm for Field Programmable Gate Array
17.1. INTRODUCTION
17.2. PLACING AND ROUTING
17.3. PARTITIONING ALGORITHM
17.4. KERNIGHAN-LIN ALGORITHM
17.4.1. How K-L Works
17.4.2. Implementation of K-L Algorithm
17.4.3. Steps of Algorithm
17.5. SUMMARY
CHAPTER 18: LUT-Based BCD Multiplier Design
18.1. INTRODUCTION
18.2. BASIC PROPERTIES
18.3. THE ALGORITHM
18.3.1. The BCD Multiplication Method
18.3.2. The LUT Architecture
18.4. LUT-BASED BCD MULTIPLIER CIRCUIT
18.5. SUMMARY
CHAPTER 19: LUT-Based Matrix Multiplier Circuit Using Pigeonhole Principle
19.1. INTRODUCTION
19.2. BASIC DEFINITIONS
19.2.1. Binary Multiplication
19.2.2. Matrix Multiplication
19.2.3. BCD Coding
19.2.4. BCD Addition
19.2.5. Binary to BCD Conversion
19.2.6. Pigeonhole Principle
19.2.7. Field Programmable Gate Arrays
19.2.8. Look-Up Table
19.2.9. LUT-Based Adder
19.2.10. BCD Adder
19.2.11. Comparator
19.2.12. Shift Register
19.2.13. Literal Cost
19.2.14. Gate Input Cost
19.2.15. Xilinx Virtex 6 FPGA Slice
19.3. THE MATRIX MULTIPLIER
19.3.1. The Efficient Matrix Multiplication Method
19.3.1.1. The (1 x 1)-Digit Multiplication Algorithm
19.3.1.2. The (mxn)-Digit Multiplication Algorithm Using the (1 x 1)-Digit Multiplication Algorithm
19.3.1.3. Binary to BCD Conversion Algorithm
19.3.1.4. Efficiency of the (mxn)-Digit Multiplication Algorithm
19.3.2. The Matrix Multiplication Algorithm
19.3.3. The Cost-Efficient Matrix Multiplier Circuit
19.3.3.1. (1 x 1)-Digit Multiplier Circuit
19.3.3.2. Binary to BCD Converter Circuit for the Decimal Multiplier
19.3.3.3. (mxn )-Digit Multiplier Circuit
19.3.3.4. Matrix Multiplier Circuit
19.4. SUMMARY
CHAPTER 20: BCD Adder Using a LUT-Based Field Programmable Gate Array
20.1. INTRODUCTION
20.2. BCD ADDER USING LUTS
20.2.1. The BCD Addition Method
20.2.2. The Architecture of a LUT
20.2.2.1. Working Mechanism of the 2-Input LUT
20.3. BCD ADDER CIRCUIT USING LUTS
20.4. SUMMARY
CHAPTER 21: Generic Complex Programmable Logic Device Board
21.1. INTRODUCTION
21.2. HARDWARE DESIGN AND DEVELOPMENT
21.2.1. DC-DC Converters
21.2.2. JTAG Interface
21.2.3. LED Interface
21.2.4. Clock Circuit
21.2.5. CPLD
21.2.6. Seven-Segment Display
21.2.7. Input/Output Connectors
21.3. INTERNAL HARDWARE DESIGN OF CPLD
21.3.1. A5/1. Algorithm
21.3.2. Seven Segment Display Driver
21.3.3. Binary 8-Bit Counter
21.4. APPLICATIONS
21.5. SUMMARY
CHAPTER 22: FPGA-Based Programmable Logic Controller
22.1. INTRODUCTION
22.2. FPGA TECHNOLOGY FOR PLC
22.3. SYSTEM DESIGN PROCEDURE FOR PLC
22.3.1. Ladder Program Structure
22.3.2. Operating Modes of PLC
22.3.3. Ladder Scanning
22.3.4. Ladder Execution
22.3.5. System Implementation
22.4. DESIGN CONSIDERATIONS
22.5. SUMMARY
SECTION IV: An Overview About Design Architectures of Digital Circuits
Part 4
CHAPTER 23: Parallel Computation of Quotients and Partial Remainders to Design Divider Circuits
23.1. INTRODUCTION
23.2. BASIC DEFINITIONS
23.2.1. Division Operation
23.2.2. Shift Registers
23.2.2.1. Serial-In to Parallel-Out Shift Register
23.2.2.2. Serial-In to Serial-Out Shift Register
23.2.2.3. Parallel-In Serial-Out Register
23.2.2.4. Parallel-In to Parallel-Out Shift Register
23.2.3. Complement Logic
23.2.4. Comparator
23.2.5. Adder
23.2.6. Subtractor
23.2.7. Look-Up Table
23.2.8. Counter Circuit
23.2.9. Reversible and Fault Tolerance Logic
23.3. THE METHODOLOGIES
23.3.1. Division Algorithm
23.3.1.1. Explanation of Correctness of the Division Algorithm
23.3.2. ASIC-Based Circuits
23.3.2.1. Parallel n-bit Counter Circuit
23.3.2.2. n-bit Comparator
23.3.2.3. n-bit Selection Block
23.3.2.4. Circuit for Conversion to Zero
23.3.2.5. Design of the Divider Circuit
23.3.3. LUT-Based Circuits
23.3.3.1. LUT-Based Bit Counter Circuit
23.3.3.2. LUT-Based Bit Comparator Circuit
23.3.3.3. LUT-Based Selection Circuit
23.3.3.4. LUT-Based Converter Circuit
23.3.3.5. Design of the LUT-Based Divider Circuit
23.3.3.6. Reversible Fault Tolerant LUT-Based Divider Circuit
23.4. SUMMARY
CHAPTER 24: Synthesis of Boolean Functions Using TANT Networks
24.1. INTRODUCTION
24.2. TANT MINIMIZATION
24.2.1. The Technique
24.3. THE INTRODUCED METHOD OF TANT MINIMIZATION
24.4. ALGORITHMS USED IN DIFFERENT STAGES
24.5. SUMMARY
CHAPTER 25: Asymmetric High Radix Signed Digital Adder Using Neural Networks
25.0.1. Introduction
25.1. BASIC DEFINITIONS
25.1.1. Neural Network
25.1.2. Asymmetric Number System
25.1.3. Binary to Asymmetric Number System Conversion
25.1.4. Addition of AHSD4 Number System
25.2. THE DESIGN OF ADDER USING NEURAL NETWORK
25.3. AHSD ADDITION FOR RADIX-5
25.4. SUMMARY
CHAPTER 26: Wrapper/TAM Co-Optimization and Constrained Test Scheduling
26.1. INTRODUCTION
26.2. THE WRAPPER DESIGN
26.3. TAM DESIGN AND TEST SCHEDULING
26.4. POWER CONSTRAINED TEST SCHEDULING
26.4.1. Data Structure
26.4.2. Rectangle Construction
26.4.3. Diagonal Length Calculation
26.4.4. TAM Assignment
26.5. SUMMARY
CHAPTER 27: Static Random Access Memory Using Memristor
27.1. INTRODUCTION
27.2. MEMRISTOR CHARACTERIZATION
27.3. MEMRISTOR AS A SWITCH
27.4. WORKING PRINCIPLE OF MEMRISTOR
27.5. MEMRISTOR-BASED SRAM
27.6. SUMMARY
CHAPTER 28: A Fault Tolerant Approach to Microprocessor Design
28.1. INTRODUCTION
28.1.1. Design Faults
28.1.2. Manufacturing Defects
28.1.3. Operational Faults
28.2. DYNAMIC VERIFICATION
28.2.1. System Architecture
28.2.2. Checker Processor Architecture
28.3. PHYSICAL DESIGN
28.4. DESIGN IMPROVEMENTS FOR ADDITIONAL FAULT COVERAGE
28.4.1. Operational Errors
28.4.2. Manufacturing Errors
28.5. SUMMARY
CHAPTER 29: Applications of VLSI Circuits and Embedded Systems
29.1. APPLICATIONS OF VLSI CIRCUITS
29.1.1. Autonomous Robots in Industrial Plants
29.1.2. Machines in Manufacturing
29.1.3. Smart Vision Tech for Quality Control
29.1.4. Wearables: Ensuring Security
29.1.5. Computing Using the CPU
29.1.6. System on a Chip
29.1.7. Cutting Edge AI Handling
29.1.8. VLSI in 5G Networks
29.1.9. Fuzzy Logic and Decision Diagrams
29.2. APPLICATION OF EMBEDDED SYSTEMS
29.2.1. Embedded System for Street Light Control
29.2.2. Embedded System for Industrial Temperature Control
29.2.3. Embedded System for Traffic Signal Control
29.2.4. Embedded System for Vehicle Tracking
29.2.5. Embedded System for War Field Spying Robot
29.2.6. Automated Vending Machine
29.2.7. Mechanical Arm Regulator
29.2.8. Routers and Switches
29.2.9. Industrial Field Programmable Gate Arrays
29.2.10. Industrial Programmable Logic Circuits
29.3. SUMMARY
VLSI Circuits and Embedded Systems
Index