In this article, an asynchronous array architecture for straight line Hough transform (HT) is proposed using a scaling-free modi"ed Co-Ordinate Rotation Digital Computer (CORDIC) unit as a basic processing element (PE). It exhibits four-fold angle parallelism by dividing the Hough space into four su
โฆ LIBER โฆ
VLSI architecture for the Winograd Fourier transform algorithm
โ Scribed by B. Gopal; S. Manohar
- Publisher
- Elsevier Science
- Year
- 1994
- Weight
- 659 KB
- Volume
- 40
- Category
- Article
- ISSN
- 0165-6074
No coin nor oath required. For personal study only.
๐ SIMILAR VOLUMES
A VLSI array architecture for Hough tran
โ
K. Maharatna; Swapna Banerjee
๐
Article
๐
2001
๐
Elsevier Science
๐
English
โ 162 KB
The connection between algorithms of the
โ
O.M. Makarov
๐
Article
๐
1975
๐
Elsevier Science
โ 714 KB
Fourier transform algorithms for interfe
โ
Horst Ziegler
๐
Article
๐
1975
๐
Elsevier Science
โ 492 KB
A bit-serial VLSI architecture for the 2
โ
Anna Tatsaki; Costas Goutis
๐
Article
๐
1994
๐
Elsevier Science
โ 887 KB
Generic VLSI architecture for block-matc
โ
Zhong L. He; Ming L. Liou; Philip. C. H. Chan; C. Y. Tsui
๐
Article
๐
1998
๐
John Wiley and Sons
๐
English
โ 403 KB
In this article, a generic VLSI architecture which is both a switch network to implement two block-matching motion estiprogrammable and scalable is proposed for block-matching motion mation algorithms: namely, full-search and three-step search, estimation algorithms. Various motion estimation algori
New algorithms for calculating discrete
โ
A.M. Grigoryan
๐
Article
๐
1986
๐
Elsevier Science
โ 516 KB