Generic VLSI architecture for block-matching motion estimation algorithms

✍ Scribed by Zhong L. He; Ming L. Liou; Philip. C. H. Chan; C. Y. Tsui

• Publisher: John Wiley and Sons
• Year: 1998
• Tongue: English
• Weight: 403 KB
• Volume: 9
• Category: Article
• ISSN: 0899-9457
• DOI: 10.1002/(sici)1098-1098(1998)9:4<257::aid-ima8>3.0.co;2-9

✦ Synopsis

In this article, a generic VLSI architecture which is both a switch network to implement two block-matching motion estiprogrammable and scalable is proposed for block-matching motion mation algorithms: namely, full-search and three-step search, estimation algorithms. Various motion estimation algorithms can be only for low-bit-rate applications. The design in [26] uses a implemented using the proposed architecture by organizing the indidistributed programmable motion estimator architecture and optividual search positions (checking points) into checking vectors. A

mizes its processing engine for hardware efficiency and the conchecking vector is processed in parallel by fully exploiting its data trol engine for flexibility. The distributed architecture models dependency. The optimal choice for the size of checking vector is motion estimation as if searching through a tree of vector points, discussed based on the design tradeoffs among processing speed, where the traversing functions are implemented in a multimode silicon area, and I/O bandwidth. Appropriate designs are recomvector search engine and the hierarchy is constructed by an algomended for various video applications.