Cover
Contents
About the editors
Preface
Acknowledgments
Section I. Low voltage and low power VLSI design
1 Low-voltage analog signal processing
1.1 Current-mode circuits
1.1.1 Current conveyors
1.2 Low-voltage design techniques
1.2.1 Subthreshold MOSFETs
1.2.2 Bulk-driven MOSFETs
1.2.3 Split-length MOSFETs
1.2.4 Floating-gate MOSFETs
1.2.5 Flipped voltage follower
1.3 CMOS analog cells
1.4 Current mirrors
1.4.1 Equivalent circuit of the current mirror
1.4.2 Source degenerated current mirror
1.4.3 Cascode current mirror
1.4.4 Wilson current mirror
1.4.5 Improved Wilson current mirror
1.4.6 Wide-swing current mirror
1.4.7 Enhanced output impedance current mirror
1.4.8 Level shifted low voltage CM
1.5 Summary
References
2 Negative bias temperature instability (NBTI) aware low leakage circuit design
2.1 Introduction
2.2 Techniques for NBTI mitigation
2.2.1 Input vector control
2.2.2 Gate-replacement method
2.2.3 Adaptive power supply
2.2.4 Body biasing
2.2.5 Gate-sizing technique
2.2.6 Power-gating technique
2.2.7 Aging-monitoring techniques
2.3 Summary
References
3 Low-voltage, low-power SRAM circuits using subthreshold design technique
3.1 Introduction
3.2 Design and operation of C6T
3.3 Design and operation of proposed SRAM cells at 45 nm
3.3.1 Design of proposed MPT8T using PN access transistor
3.3.2 Design of proposed M8T using NN-parallel access transistor
3.3.3 Design of proposed MI-12T
3.3.4 Design of proposed M7T
3.3.5 Design of proposed M9T
3.4 Results and analysis
3.4.1 SRAM standby stability analysis (hold stability)
3.4.2 SRAM read stability analysis
3.4.3 SRAM write ability analysis
3.4.4 Alternative noise margins
3.4.5 Read access time (TRA) with variability
3.4.6 Write access time (TWA) with variability
3.4.7 Leakage power consumption in hold mode
3.5 Analytical expressions for hold SNM, RSNM and WSNM of SRAM cells
3.6 Performance analysis and discussion
3.7 Summary
References
4 Design and analysis of memristor-based DRAM cell for low-power application
4.1 Introduction to memristor
4.1.1 Memristor overview
4.1.2 Memristance
4.1.3 Types of memristor
4.1.4 Working of memristor
4.1.5 Fingerprints of memristor
4.1.6 Fabrication steps of memristor
4.1.7 Models of memristor
4.1.7.1 Linear ion drift model
4.1.7.2 Nonlinear ion drift model
4.1.7.3 Simmons tunnel model
4.1.7.4 TEAM memristor model
4.1.8 Application and properties of memristor
4.2 Memristor and transmission gate-based DRAM cell
4.2.1 Introduction to transmission gates
4.2.2 Overview of semiconductor memories
4.2.2.1 Volatile memory
4.2.2.2 Nonvolatile memory
4.2.2.3 Why memristor-based memories?
4.2.3 Design of memristor and transmission gate-based DRAM cell
4.2.3.1 Design methodology
4.2.3.2 Read and write operation
4.3 Simulation results
4.3.1 Validation of memristor model
4.3.2 Simulation result of memristor and transmission-gate-based DRAM cell
4.3.3 Comparison of results
4.4 Summary
References
5 Design of a novel tunnel FET for low-power applications
5.1 Introduction
5.2 Basic structure and principle of operation
5.3 Band diagrams
5.4 Analytical models in TFET
5.5 Tunnel FET electrical parameters
5.5.1 ON current
5.5.2 OFF current
5.5.3 Gate threshold voltage
5.5.4 Drain threshold voltage
5.5.5 Transconductance
5.5.6 Output conductance
5.5.7 ION/IOFF ratio
5.5.8 Capacitance
5.5.9 Subthreshold swing
5.6 Various TFET architectures
5.7 Applications of TFET
5.7.1 Complementary TFET
5.7.2 Application as biosensor
5.8 Summary
References
6 Composite PFD based low-power, low noise, fast lock-in PLL
6.1 Proposed composite PFD architecture
6.1.1 Transistor level implementation of NL-PFD3
6.1.2 Transistor level implementation of L-PFD3
6.2 Proposed PLL architecture
6.2.1 Charge pump and VCO in the PLL
6.3 Design of novel PLL architecture using composite PFD and variable loop filter
6.4 State-space analysis of PLL architecture
6.5 Post layout simulation analysis of novel PLL architecture
6.5.1 Trade-off between power and frequency
6.5.2 Lock-time analysis
6.5.3 Phase-noise analysis of novel PLL architecture
6.5.4 Reference spur
6.5.5 Jitter
6.5.6 PVT analysis of proposed PLL
6.5.7 Discussion
6.6 Summary
References
Section II. Modelling and simulation for post-CMOS device and circuit design
7 Emerging devices beyond CMOS: fundamentals, promises and challenges
7.1 Charge-based devices
7.1.1 Tunnel field-effect transistors
7.1.2 Negative capacitance field-effect transistors
7.1.3 Mott FET or phase FET
7.1.4 Nano-electro-mechanical switches
7.2 Non-charge-based devices
7.2.1 Spin-wave device
7.2.2 Nanomagnetic logic
7.2.3 All spin logic
7.2.4 Probabilistic spin logic
7.3 Summary
References
8 Two-dimensional material-based field-effect transistors for post-silicon electronics
8.1 Introduction
8.1.1 Transistor figure of merits and trade-off
8.1.2 2-D materials for electronics: state-of-art and challenges
8.2 Modelling approach
8.3 Energy gap and carrier mobilities
8.4 Digital performance
8.4.1 Transfer and output characteristics
8.4.2 Benchmarking of digital figure-of-merits
8.5 Analog/RF performance
8.5.1 Intrinsic analog/RF performance metrics
8.5.2 RF performance with parasitics
8.5.3 Benchmarking of analog/RF FOMs
8.6 Summary
References
9 Theory and modelling of spin-transfer-torque based electronic devices
9.1 Introduction
9.2 The spin valve or magnetic tunnel junction
9.3 The LandauโLifshitzโGilbertโSlonczewski equation
9.4 Circuit model for spin transport
9.4.1 Decoupling charge and spin
9.4.2 Diffusion equations in the chargeโspin basis
9.4.3 Lumped circuit models for spinโcharge representation
9.4.3.1 Ferromagnetic material
9.4.3.2 Nonmagnetic material
9.4.3.3 Interface
9.5 Spin accumulation at the interface between a magnetic and nonmagnetic material
9.5.1 An example of RTMTJ
9.6 Generation of spin current
9.7 All-spin logic gate
9.8 Other directions in spin-based computations
References
10 Spintronics memory and logic: an efficient alternative to CMOS technology
10.1 Introduction
10.2 Thrust for emerging nonvolatile memories
10.3 Basics of spintronics
10.3.1 Giant magnetoresistance
10.3.2 Tunneling magnetoresistance
10.3.3 Spin-transfer torque
10.4 Magnetic tunnel junction
10.4.1 In-plane MTJ
10.4.2 Perpendicular plane MTJ
10.5 Spin-transfer torque magnetic random-access memory
10.5.1 Write operation
10.5.2 Read operation
10.5.3 Performance parameters
10.5.4 Challenges for STT-MRAM
10.6 Simulation setup
10.7 Spintronics-based hybrid MTJ/CMOS circuits
10.7.1 Precharged sense amplifier
10.7.2 Write circuit
10.8 Hybrid MTJ/CMOS logic circuits
10.8.1 Hybrid MTJ/CMOS AND/NAND gate
10.8.2 Hybrid MTJ/CMOS OR/NOR gate
10.8.3 Hybrid MTJ/CMOS XOR/XNOR gate
10.9 Magnetic nonvolatile full adder
10.10 Device-to-system level
10.11 Summary
References
11 Tunneling field effect transistors for energy efficient digital, RF and power management circuit designs enabling IoT edge computing platforms
11.1 Tunnel FET device structure, characteristics, and models
11.1.1 Tunnel FET device structure and models
11.1.2 Tunnel FET device characteristics
11.1.2.1 Transfer characteristics (IDโVGS) and subthreshold swing
11.1.2.2 Output characteristics and unidirectional current conduction
11.1.2.3 Ambipolar and p-i-n forward leakage of InAs TFET
11.1.2.4 TFET capacitance characteristics and Miller effect
11.1.2.5 Transconductance (gm)
11.1.2.6 Current efficiency, transit frequency, and figure of merit (FoM)
11.2 TFET-based energy-efficient digital circuit design
11.2.1 TFET-based digital logic gates
11.2.1.1 Static complementary TFET inverter
11.2.1.2 DC characteristics of a TFET complementary inverter
11.2.1.3 Performance comparison of TFET logic gates with FinFET
11.2.2 Energy-efficient and reliable TFET-based digital buffers
11.2.2.1 Benchmarking of TFET buffer designs with Si FinFETs
11.2.2.2 TFET vs FinFET buffer designs with identical transistor sizes
11.2.2.3 TFET vs FinFET buffer design for Iso-energy
11.2.2.4 TFET vs FinFET buffer designs for Iso-speed
11.2.2.5 Noise margin analysis
11.2.3 Impact of TFET (InAs) ambipolarity and alternative energy-efficient logic design
11.2.3.1 Impact of p-i-n forward leakage on TFET transmission gate (TG) logic
11.2.3.2 TFET Novel logic gates
11.3 TFET-based low voltage analog and RF circuit design
11.3.1 TFET-based ring oscillator
11.3.1.1 TFET-based 3-, 5-, and 7-stage RO design and performance analysis
11.3.2 TFET voltage-controlled ring oscillator design
11.3.2.1 Performance benchmarking of TFET VCRO design
11.4 TFET-based low voltage power management circuit design
11.4.1 TFET-based digital low-dropout voltage regulator
11.5 Summary
Acknowledgment
References
12 High performing metalโoxide semiconductor thin-film transistors
12.1 Introduction
12.1.1 Review of progress in oxide TFTs
12.1.2 Review of progress in organicโinorganic hybrid complementary circuits
12.2 TFT fabrication and characterization
12.2.1 Device structure of TFTs
12.2.2 Device operation of n-channel TFTs
12.2.3 Current voltage characteristics of n-channel TFTs
12.2.4 Device characterization of n-channel TFTs
12.2.4.1 Extraction of performance parameters
12.3 Experimental methods used for fabrication of TFTs
12.3.1 Thermal evaporation
12.3.2 Fabrication steps for oxide semiconductor solution process
12.4 Development of high-k gate dielectric (Al2O3) and sputtered ZnO TFTs
12.4.1 Comparison of sputtered and sprayed ZnO TFTs
12.4.2 IGZO TFT performance investigation using Taguchi orthogonal arrays
12.5 Understanding ZnO TFT UV sensor performance using Taguchi OA
Acknowledgment
References
13 CNTFETs: modelling and circuit design
13.1 Introduction
13.2 Carbon nanotubes: material science and application as channel in FET
13.3 Types of CNTFETs
13.4 Electrostatic doping
13.5 Simulation tool and results
13.6 Modelling styles
13.7 CNTFET-based circuit design
13.8 Summary
13.9 Future scope
References
Index
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