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Unified Architecture for Double/Two-Parallel Single Precision Floating Point Adder

✍ Scribed by Jaiswal, Manish Kumar; Cheung, Ray C. C.; Balakrishnan, M.; Paul, Kolin

Book ID: 127077019
Publisher: Institute of Electrical and Electronics Engineers
Year: 2014
Tongue: English
Weight: 476 KB
Volume: 61
Category: Article
ISSN: 1549-7747
DOI: 10.1109/tcsii.2014.2327314

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