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[IEEE 2007 IEEE International Conf. on Application-specific Systems, Architectures and Processors - Montreal, QC, Canada (2007.07.9-2007.07.11)] 2007 IEEE International Conf. on Application-specific Systems, Architectures and Processors (ASAP) - An FPGA Implementation of a Fully Verified Double Precision IEEE Floating-Point Adder

✍ Scribed by Kikkeri, Nikhil; Seidel, Peter-Michael

Book ID: 126620206
Publisher: IEEE
Year: 2007
Weight: 352 KB
Category: Article
ISBN: 1424410274
DOI: 10.1109/ASAP.2007.4429962

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