Thermal studies on pin grid array packages for high density LSI and VLSI logic circuits: L. Mali mahalingham, James A. Andrews and James E. Drye IEEE Trans. Components Hybrids Mfg Technol. Chmt-6 (3), 246 (September 1983)

• Book ID: 104157255
• Publisher: Elsevier Science
• Year: 1985
• Tongue: English
• Weight: 180 KB
• Volume: 16
• Category: Article
• ISSN: 0026-2692
• DOI: 10.1016/s0026-2692(85)80034-3

✦ Synopsis

An analytical method is described which provides estimates to first ordel of the number of either power or environmental cycle's leading to solder joint failure. Various parameter variations such as solder joint height, ceramic chip carrier (CCC) size, printed circuit substrate (PCS) material, etc. are investigated and discussed and sample estimates for a 0.65 x 0.65-in CCC are given.

High pinout IC packaging and the density advantage of surface mounting WULF H. KNAUSENBERGER and NICHOLAS A. TENEKETGES.