A restructurable (reconfigurable) parallel VLSI processor designed to minimize the operation delay time which can be generally used for various operations necessary for controlling an intelligent robot was proposed previously by the authors. This processor is constructed by connecting a number of pr
โฆ LIBER โฆ
The Hypercube as a Dynamically Reconfigurable Processor Mesh
โ Scribed by Joseph M. Joy; R.Daniel Bergeron
- Publisher
- Elsevier Science
- Year
- 1998
- Tongue
- English
- Weight
- 195 KB
- Volume
- 48
- Category
- Article
- ISSN
- 0743-7315
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