The dangers of simplistic delay models

✍ Scribed by David M. Wessels; Jon C. Muzio

• Publisher: Springer US
• Year: 1996
• Tongue: English
• Weight: 706 KB
• Volume: 8
• Category: Article
• ISSN: 0923-8174
• DOI: 10.1007/bf00136076

✦ Synopsis

The identification of sensitizable paths and the determination of path delays play key roles in many delay fault testing schemes. In this paper we examine a range of gate delay models with respect to their impact on identifying both sensitizable paths and maximum circuit delays in combinational logic circuits. We provide recommendations on the "minimum acceptable" model for identifying critical paths, and a minimum acceptable model for determining maximum circuit delays. In particular, we recommend against the use of delay models which fail to distinguish between rise and fall delays. Such models, including the commonly-used "unit-delay" model, are shown to significantly misrepresent circuit delay behaviour, particularly with respect to critical paths and long false paths.