✦ LIBER ✦

Test bus sizing for system-on-a-chip

✍ Scribed by Iyengar, V.; Chakrabarty, K.

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

Design methodology for on-chip bus archi

✍ Lee, J. 📂 Article 📅 2012 🏛 The Institution of Engineering and Technology 🌐 English ⚖ 720 KB

CAS-BUS: A Test Access Mechanism and a T

✍ Mounir Benabdenbi; Walid Maroufi; Meryem Marzouki 📂 Article 📅 2002 🏛 Springer US 🌐 English ⚖ 888 KB

A System-On-Chip Bus Architecture for Th

✍ Lok-Won Kim; Villasenor, J.D. 📂 Article 📅 2011 🏛 IEEE 🌐 English ⚖ 337 KB

System-on-chip communication architectur

✍ Wang, N.; Bayoumi, M.A. 📂 Article 📅 2007 🏛 The Institution of Engineering and Technology 🌐 English ⚖ 345 KB

A hierarchical test methodology for syst

✍ Jin-Fu Li; Hsin-Jung Huang; Jeng-Bin Chen; Chih-Pin Su; Cheng-Wen Wu; Chuang Che 📂 Article 📅 2002 🏛 IEEE 🌐 English ⚖ 396 KB

Applying stochastic modeling to bus arbi

✍ Sankalp Kallakuri; Alex Doboli; Simona Doboli 📂 Article 📅 2007 🏛 Elsevier Science 🌐 English ⚖ 183 KB