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Systolic arrays for serial signal processing

✍ Scribed by Otello Bruschi; Roberto Negrini; Stefano Ravaglia

Publisher
Elsevier Science
Year
1987
Weight
451 KB
Volume
20
Category
Article
ISSN
0165-6074

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A dynamically reconfigurable bit-serial systolic array implemented in 1.2-Β΅m double-metal P-well CMOS is described. This processor array is proposed as the central computational unit in the Reconfigurable Systolic Array (RSA) neuro-computer and performance estimates suggest that a 64 IC system (cont