Systolic architecture for the VLSI implementation of high-speed staged decoders/quantizers

✍ Scribed by Caire, G. ;Ventura-Traveset, J. ;Hollreiser, M. ;Biglieri, E.

• Publisher: Springer
• Year: 1995
• Tongue: English
• Weight: 1001 KB
• Volume: 10
• Category: Article
• ISSN: 0922-5773
• DOI: 10.1007/bf02407033