<p><P><EM>"Tools alone aren't enough to reduce dynamic and leakage power in complex chip designs - a well-planned methodology is needed. Following in the footsteps of the successful Reuse Methodology Manual (RMM), authors from ARM and Synopsys have written this Low Power Methodology Manual (LPMM) to
System on Chip Interfaces for Low Power Design
β Scribed by Mishra, Sanjeeb; Rousseau, Vijayakrishnan; Singh, Neeraj Kumar
- Publisher
- Morgan Kaufmann is an imprint of Elsevier
- Year
- 2016
- Tongue
- English
- Leaves
- 389
- Edition
- 1
- Category
- Library
No coin nor oath required. For personal study only.
β¦ Synopsis
System on Chip Interfaces for Low Power Design provides a top-down understanding of interfaces available to SoC developers, not only the underlying protocols and architecture of each, but also how they interact and the tradeoffs involved. The book offers a common context to help understand the variety of available interfaces and make sense of technology from different vendors aligned with multiple standards. With particular emphasis on power as a factor, the authors explain how each interface performs in various usage scenarios and discuss their advantages and disadvantages. Readers learn to make educated decisions on what interfaces to use when designing systems and gain insight for innovating new/custom interfaces for a subsystem and their potential impact.
- Provides a top-down guide to SoC interfaces for memory, multimedia, sensors, display, and communication
- Explores the underlying protocols and architecture of each interface with multiple examples
- Guides through competing standards and explains how different interfaces might interact or interfere with each other
- Explains challenges in system design, validation, debugging and their impact on development
β¦ Table of Contents
Content:
Front Matter,Copyright,Copyright Permissions,Dedication,AcknowledgmentsEntitled to full textChapter 1 - SoC Design Fundamentals and Evolution, Pages 1-11
Chapter 2 - Understanding Power Consumption Fundamentals, Pages 13-27
Chapter 3 - Generic SoC Architecture Components, Pages 29-51
Chapter 4 - Display Interfaces, Pages 53-126
Chapter 5 - Multimedia Interfaces, Pages 127-237
Chapter 6 - Communication Interfaces, Pages 239-273
Chapter 7 - Memory Interfaces, Pages 275-305
Chapter 8 - Security Interfaces, Pages 307-317
Chapter 9 - Power Interfaces, Pages 319-330
Chapter 10 - Sensor Interfaces, Pages 331-344
Chapter 11 - Input Device Interfaces, Pages 345-357
Chapter 12 - Debug Interfaces, Pages 359-366
Appendix A - Overview of Intel SoC: Baytrail, Pages 367-370
Appendix B - Industry Consortiums, Pages 371-373
Appendix C - USB 3.0, Pages 375-380
Appendix D - USB OTG (On The Go), Pages 381-382
References, Pages 383-384
Index, Pages 385-392
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