โ Scribed by Z. Peng, M. Sonza Reorda, M. Violante (auth.), Professor Matteo Sonza Reorda, Professor Zebo Peng, Dr. Massimo Violante (eds.)
No coin nor oath required. For personal study only.
New manufacturing technologies have made possible the integration of entire systems on a single chip. This new design paradigm, termed system-on-chip (SOC), together with its associated manufacturing problems, represents a real challenge for designers.
As well as giving rise to new design practices, SOC is also reshaping approaches to test and validation activities. These are beginning to migrate from the traditional register-transfer or gate levels of abstraction to the system level. Until now, test and validation have not been supported by system-level design tools so designers have lacked the necessary infrastructure to exploit all the benefits stemming from the adoption of the system level of abstraction such as higher functional performance and greater operating speed. Research efforts are already addressing this issue.
System-level Test and Validation of Hardware/Software Systems provides a state-of-the-art overview of the current validation and test techniques by covering all aspects of the subject including:
โข modeling of bugs and defects;
โข stimulus generation for validation and test purposes (including timing errors;
โข design for testability.
For researchers working on system-level validation and testing, for tool vendors involved in developing hardware-software co-design tools and for graduate students working in embedded systems and SOC design and implementation, System-level Test and Validation of Hardware/Software Systems will be an invaluable source of reference.
Introduction....Pages 1-3
Modeling Permanent Faults....Pages 5-25
Test Generation: A Symbolic Approach....Pages 27-46
Test Generation: A Heuristic Approach....Pages 47-65
Test Generation: A Hierarchical Approach....Pages 67-81
Test Program Generation from High-level Microprocessor Descriptions....Pages 83-106
Tackling Concurrency and Timing Problems....Pages 107-120
An Approach to System-level Design for Test....Pages 121-149
System-level Dependability Analysis....Pages 151-174
Circuits and Systems; Electronics and Microelectronics, Instrumentation; Engineering Design; Computer Hardware; Programming Techniques; Condensed Matter
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"System-level Test and Validation of Hardware/Software Systems provides a state-of-the-art overview of the current validation and test techniques by covering all aspects of the subject including: modeling of bugs and defects; stimulus generation for validation and test purposes (including timing err
<p>This book covers state-of-the art techniques for high-level modeling and validation of complex hardware/software systems, including those with multicore architectures. Readers will learn to avoid time-consuming and error-prone validation from the comprehensive coverage of system-level validation,
<p>Modern embedded systems require high performance, low cost and low power consumption. Such systems typically consist of a heterogeneous collection of processors, specialized memory subsystems, and partially programmable or fixed-function components. This heterogeneity, coupled with issues such as
<p>Modern embedded systems require high performance, low cost and low power consumption. Such systems typically consist of a heterogeneous collection of processors, specialized memory subsystems, and partially programmable or fixed-function components. This heterogeneity, coupled with issues such as