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Synthesis of Sequential Circuits by Redundancy Removal and Retiming

✍ Scribed by Hiroyuki Yotsuyanagi; Seiji Kajihara; Kozo Kinoshita

Book ID
110260809
Publisher
Springer US
Year
1997
Tongue
English
Weight
136 KB
Volume
11
Category
Article
ISSN
0923-8174

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## Abstract This paper proposes a method for efficiently removing redundant elements using properties of undetectable faults obtained by test pattern generation. Lines of redundant elements have undetectable single stuck‐at faults. We classify undetectable faults into three categories according to