𝔖 Bobbio Scriptorium
✦   LIBER   ✦

Subthreshold characteristics of DMOS and CMOS transistors in high voltage BCDMOS technology

✍ Scribed by C.Y. Lu; M.C. Morgan; N.S. Tsai


Publisher
Elsevier Science
Year
1987
Tongue
English
Weight
517 KB
Volume
30
Category
Article
ISSN
0038-1101

No coin nor oath required. For personal study only.


📜 SIMILAR VOLUMES


Optimization of a very cost-effective hi
✍ A. Pérez-Tomás; X. Jordà; P. Godignon 📂 Article 📅 2005 🏛 Elsevier Science 🌐 English ⚖ 682 KB

This paper discusses the optimization and fabrication of a high voltage p-channel extended drain MOSFET (ED-pMOSFET) using standard low cost 2.5 lm twin-tub CMOS technology for digital applications, with only one extra processing step. The ED-pMOSFET transistor has been optimized using 2D simulators

Design and characterization of high-volt
✍ Xiaoliang Han; Chihao Xu 📂 Article 📅 2007 🏛 Elsevier Science 🌐 English ⚖ 281 KB

This paper presents the design of high-voltage NMOS and PMOS devices with shallow trench isolation (STI) in standard 0.25 mm/5 V CMOS technology. Breakdown voltages of 20 V for n-channel device with a specific on resistance of 1.06 mO cm 2 and À20 V for p-channel device with a specific on resistance