Sub-1/4-μm dual-gate CMOS technology using in-situ doped polysilicon for nMOS and pMOS gates

✍ Scribed by Okazaki, Y.; Kobayashi, T.; Inokawa, H.; Nakayama, S.; Miyake, M.; Morimoto, T.; Yamamoto, Y.

• Book ID: 114536150
• Publisher: IEEE
• Year: 1995
• Tongue: English
• Weight: 773 KB
• Volume: 42
• Category: Article
• ISSN: 0018-9383
• DOI: 10.1109/16.405271