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SPIDER: capacitance modelling for VLSI interconnections

✍ Scribed by Ning, Z.-Q.; Dewilde, P.M.

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

Three-dimensional capacitance computatio

✍ Zemanian, A.H.; Tewarson, R.P.; Ju, C.P.; Jen, J.F. 📂 Article 📅 1989 🏛 IEEE 🌐 English ⚖ 832 KB

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✍ Shyh-Chyi Wong, ; Gwo-Yann Lee, ; Dye-Jyun Ma, 📂 Article 📅 2000 🏛 IEEE 🌐 English ⚖ 140 KB

A `missing neighbor model' for capacitiv

✍ Smith, W.R.; Powell, S.; Persky, G. 📂 Article 📅 1987 🏛 IEEE 🌐 English ⚖ 602 KB

Inductance and capacitance analytic form

✍ Delorme, N.; Belleville, M.; Chilo, J. 📂 Article 📅 1996 🏛 The Institution of Electrical Engineers 🌐 English ⚖ 215 KB

The per-unit-length capacitance matrix o

✍ Omer, A.A.; Cangellaris, A.C.; Mechaik, M.M.; Prince, J.L. 📂 Article 📅 1991 🏛 IEEE 🌐 English ⚖ 564 KB

Interconnections technologies for VLSI c

✍ Santi, Giorgio De 📂 Article 📅 1990 🏛 John Wiley and Sons 🌐 English ⚖ 546 KB