Soft Errors in Modern Electronic Systems

✍ Scribed by Nicolaidis, Michael(Editor)

• Publisher: Springer US
• Year: 2010;2011
• Tongue: English
• Leaves: 331
• Series: Frontiers in Electronic Testing 41
• Edition: 1. ed
• Category: Library

✦ Synopsis

This book provides a comprehensive presentation of the most advanced research results and technological developments enabling understanding, qualifying and mitigating the soft errors effect in advanced electronics, including the fundamental physical mechanisms of radiation induced soft errors, the various steps that lead to a system failure, the modelling and simulation of soft error at various levels (including physical, electrical, netlist, event driven, RTL, and system level modelling and simulation), hardware fault injection, accelerated radiation testing and natural environment testing, soft error oriented test structures, process-level, device-level, cell-level, circuit-level, architectural-level, software level and system level soft error mitigation techniques.

The book contains a comprehensive presentation of most recent advances on understanding, qualifying and mitigating the soft error effect in advanced electronic systems, presented by academia and industry experts in reliability, fault tolerance, EDA, processor, SoC and system design, and in particular, experts from industries that have faced the soft error impact in terms of product reliability and related business issues and were in the forefront of the countermeasures taken by these companies at multiple levels in order to mitigate the soft error effects at a cost acceptable for commercial products. In a fast moving field, where the impact on ground level electronics is very recent and its severity is steadily increasing at each new process node, impacting one after another various industry sectors (as an example, the Automotive Electronics Council comes to publish qualification requirements on soft errors), research and technology developments and industrial practices have evolve very fast, outdating the most recent books edited at 2004.

✦ Table of Contents

10.2.1 Internet Core Network Requirements......Page 3
6.2.1.2 Laser Methods......Page 5
Foreword......Page 6
9.2.3.2 Simultaneous Multithreading......Page 9
10.3.1 Memories......Page 11
10.3.2 Flip-Flops......Page 13
10.3.2.3 Device Model, Fault Model, and Stimulus......Page 15
10.3.2.4 Results Checking......Page 17
Cover......Page 1
References......Page 7
Preface......Page 10
Acknowledgments......Page 14
Contents......Page 16
1.1 Introduction......Page 20
10.3.3 Model Results......Page 21
1.2 History......Page 22
10.5 Conclusions......Page 24
10.2 System Soft Error Specification......Page 2
Soft Errors in Modern Electronic Systems......Page 4
9.2.3.1 Time Redundancy......Page 8
Purpose......Page 12
Contributors......Page 18
10.3.2.5 ASIC Case Study......Page 19
8.5 Memory Protection Using Built-In Current Sensors......Page 23
References......Page 25
1.3 Soft Errors in Electronic Systems......Page 26
9.4.4.1 Detecting and Correcting Transient Faults Affecting Data......Page 28
1.4 Scaling Trends......Page 29
1.4.1 Scaling of SRAM SER......Page 30
References......Page 31
1.4.2 Scaling of DRAM SER......Page 33
1.4.3 SER of Latches and Flip-Flops......Page 35
Further Reading......Page 38
Design of Fault Secure Functional Blocks......Page 32
Fault Secure Design Using Unordered Codes......Page 34
Efficient Circuit-Level Time Redundancy......Page 36
Chapter 2: Single Event Effects: Mechanisms and Classification......Page 45
2.1 Introduction......Page 46
1.4.4 SER of Combinational Logic......Page 39
1.4.5 Scaling of Single-Event Latchup......Page 40
1.4.6 Future Trends......Page 41
1.5 Conclusions......Page 43
2.2.1 Natural Radiation Environment......Page 47
2.2.2.1 Interaction Probability......Page 48
2.2.2.3 Nonelastic Interaction......Page 49
2.2.2.6 Nuclear Data Base......Page 50
2.2.3 Recoils: Ionization and Ranges......Page 51
2.2.3.1 Ranges of Recoils......Page 52
2.2.3.2 Velocity of Ions......Page 53
2.2.4.2 Generation Time Profile......Page 55
2.2.5 Conclusion......Page 56
2.3.3 Critical Charge Criteria......Page 57
2.3.3.1 Orders of Magnitude of Critical Charge......Page 59
2.4 Sensitivity of Devices......Page 60
2.4.1 SET......Page 61
2.4.2 SEU......Page 62
2.4.2.1 SRAM......Page 63
2.4.2.2 Upset by Direct Proton Ionization......Page 64
2.4.2.3 DRAM and SDRAM......Page 65
2.4.3 MCU and MBU in SRAM and DRAM......Page 66
2.4.4.2 SEFI in FPGA......Page 67
2.4.5.1 Latch-Up Triggering Mechanisms......Page 69
2.4.5.2 Design Rules Effects on SEL Sensitivity......Page 70
3.1 Introduction......Page 73
3.1.1 Purpose of the JESD89 Series Standards......Page 74
3.2.1 Alpha Particle Energy Spectra and Emissivity (JESD89A Annex D)......Page 76
3.2.2 Alpha Source Selection (JESD89A Sect.5.4.1 and JESD89-2A Sect.4.2.2.1)......Page 79
3.2.5 Limitations and Strengths of the Accelerated Alpha Particle Test......Page 80
3.3.1 Terrestrial High Energy Neutron Flux and Spectra (JESD89A Sect.6.6.2.4)......Page 81
3.3.2 Scaling of Reference Spectrum to Other Locations and Conditions (JESD89A Annex A.3)......Page 82
3.3.4 Packaging/Sample Preparation and Secondary Ion Effects (JESD89-3A Sect.5.4 and Annex A)......Page 83
3.3.5 Beam Characteristics (JESD89A Sect.6.5)......Page 84
3.3.7 Soft Error Rate from Broad Spectrum Neutron Beam (JESD89A 6.6.2.4)......Page 85
3.3.8 Limitations and Strengths of the Accelerated High-Energy Neutron Test......Page 86
3.4.1 Background (JESD89A Sect.7.1)......Page 87
3.4.4 Thermal Neutron Sources: Selection, Calibration and Shielding Effects (JESD89A Sect.7.4)......Page 88
3.4.6 Limitations and Strengths of the Accelerated Thermal Neutron Test......Page 89
3.5.3 Separating the Alpha and Neutron Contributions to SER......Page 90
3.5.6 Minimum FIT and Confidence Levels (JESD89A Annex C)......Page 91
3.5.7 Limitations and Strengths of the Real-Time Test......Page 92
3.6 Conclusions......Page 93
References......Page 94
4.1 Introduction......Page 95
4.2 From Nuclear Interactions to Transient Current Computation by Monte Carlo Selection of Nuclear Reactions and Device Simula.......Page 98
4.2.1 Database of Neutrons/Matter Nuclear Interactions......Page 99
4.2.2 Transient Currents Induced by Secondary Ions......Page 100
4.2.3 Example: SEU and MCU Induced by High-Energy Neutrons in SRAM......Page 102
4.3.1 The Necessity to Take into Account Multiple Transient Currents Induced by a Single Event......Page 104
4.3.2 Topological and Technological Description......Page 105
4.3.3 Nuclear Reaction Example......Page 106
4.3.4 Transient Pulse Calculation......Page 107
4.3.5 Current Pulse Statistics......Page 108
4.4.1 Collapsed Transient Currents Analysis......Page 110
4.4.2 List of Sensitive Nodes......Page 111
4.4.4 Results Analysis......Page 112
4.4.5 Example of Application on an Inverter Case......Page 113
4.4.6 Multiple Transient Fault Injection Results......Page 115
4.5 Conclusion......Page 118
References......Page 119
5.1 Introduction......Page 121
5.2.1.1 The Single-Event Transient......Page 123
5.2.1.2 The Single-Event Upset......Page 126
5.2.1.3 The Single Bit Upset, Multiple Cell Upset, and Multiple Bit Upset in Memory Blocks......Page 127
5.2.1.5 The Soft Error......Page 129
5.2.2.1 The Soft Error Rate......Page 130
5.2.3.1 Introduction......Page 131
5.2.3.3 RTL/HLS Circuit Description......Page 132
5.2.3.5 Overview......Page 133
5.3.1 Quantitative SEE Analysis......Page 134
5.3.2 Electrical Derating......Page 136
5.3.3.1 Temporal Derating for Single-Event Upsets......Page 138
5.3.3.2 Temporal Derating for Single-Event Transients......Page 141
5.3.4 Logic Derating......Page 143
5.4.1 Overview......Page 145
5.4.2 Gate-Level Netlist SEE Simulation......Page 146
5.4.3 Behavioral/RTL/HLS SEE Simulation......Page 148
5.5.1 Overview......Page 149
5.5.2.1 Combinational Cells......Page 150
5.5.2.2 Sequential Cells......Page 151
5.5.4 Architecture/Block......Page 153
References......Page 155
Further Reading......Page 158
6.1 Introduction......Page 159
6.2 Hardware Fault Injection Techniques......Page 161
6.2.1.1 Radiation Methods......Page 162
6.2.1.2 Laser Methods......Page 163
6.2.2.1 Software Implemented Fault Injection......Page 164
6.2.2.2 On-Chip Debugging for Microprocessors......Page 165
6.2.3 Logical Fault Injection by Circuit Emulation......Page 166
6.3 Fault Injection System......Page 169
6.3.1 Workload......Page 170
6.3.2 Fault List......Page 171
6.3.4 Result Analysis......Page 172
6.3.5 Communication......Page 173
6.4.1 Autonomous Emulation......Page 174
6.4.2 Fault Evaluation Process......Page 175
6.4.3 State Restoration......Page 176
6.4.4 Early Fault Classification......Page 177
6.4.5 Embedded Memories......Page 179
References......Page 182
7.1 Introduction......Page 185
7.2 Single Event Effects Due to Radiation and Their Consequences on Integrated Circuits......Page 187
7.3.1 Notion of Cross-Section......Page 188
7.3.2 Static and Dynamic SEU Test Strategies......Page 191
7.4.1 Heavy Ions......Page 193
7.4.2 Protons......Page 194
7.5.1 Introduction......Page 195
7.5.2.1 Overview......Page 196
7.6.1 SRAM Memory......Page 198
Tested Devices......Page 199
Tested Devices......Page 201
Test Conditions......Page 202
Neutron Test Results......Page 203
Neutron Tests Conclusions......Page 204
7.6.3.1 SRAM-Based FPGA Sensitive Areas......Page 206
Static Test......Page 207
Dynamic Test......Page 208
Static Test......Page 209
7.7.1 Error-Rate Prediction for an Application, a Case Study: The PPC7448......Page 210
THESIC+Daughterboard for Power PC......Page 212
Memory Controller......Page 213
Experimental Results......Page 215
Error-Rate Prediction from Different Orbits......Page 216
Heavy Ion Test Conclusions......Page 217
References......Page 218
8.1 Introduction......Page 220
8.2 Design for Soft-Error Mitigation in Memories......Page 222
8.2.1 Single-Error Correcting Double-Error Detecting Codes......Page 223
8.2.1.1 Detection of Double Errors......Page 225
8.2.1.2 Other SEC-DED Codes......Page 226
8.2.1.3 Error Detection Only......Page 227
8.2.2 Removing Speed Penalty in Memories Protected by ECC......Page 228
8.2.3 ECC Versus Non-Standard Memories......Page 233
8.3 CRC Codes......Page 235
8.4 Reed-Solomon Codes......Page 239
8.4.1 Encoding......Page 240
8.4.2 Syndrome Computation......Page 241
8.5 Memory Protection Using Built-In Current Sensors......Page 242
8.6 Error Mitigation in Logic......Page 243
8.6.1 Hardened Storage Cells......Page 244
8.6.2 SET Mitigation......Page 247
8.6.2.1 Time Redundancy Implemented in Software......Page 248
8.6.2.2 Self-Checking Design......Page 249
Fault Secure Property......Page 250
Design of Fault Secure Functional Blocks......Page 251
Fault Secure Design Using Parity Codes......Page 252
Fault Secure Design Using Unordered Codes......Page 253
Fault Secure Design Using Arithmetic Codes......Page 254
Efficient Circuit-Level Time Redundancy......Page 255
8.7 Conclusions......Page 264
References......Page 265
9.1 Introduction......Page 270
9.2.1 Computation Duplication......Page 272
9.2.2.1 Selective Procedure Call......Page 275
9.2.3.1 Time Redundancy......Page 277
9.2.3.2 Simultaneous Multithreading......Page 278
9.2.3.3 Data Diversity......Page 279
9.2.4 Executable Assertions......Page 281
9.3.1 Background......Page 282
9.3.2 ECCA......Page 283
9.3.3 CFCSS......Page 285
9.3.4 YACCA......Page 286
9.3.5 CEDA......Page 288
9.4 Addressing Fault Tolerance......Page 289
9.4.1 Design Diversity......Page 290
9.4.2 Checkpointing......Page 293
9.4.3 Algorithm-Based Fault Tolerance......Page 295
9.4.4.1 Detecting and Correcting Transient Faults Affecting Data......Page 297
9.4.4.3 Duplication and Hamming Code......Page 298
9.5 Conclusions......Page 299
References......Page 300
Chapter 10: Specification and Verification of Soft Error Performance in Reliable Electronic Systems......Page 303
10.2 System Soft Error Specification......Page 304
10.2.1 Internet Core Network Requirements......Page 305
10.2.2 Constructing the Specification......Page 309
10.3 Designing a System to Meet the Specification......Page 312
10.3.1 Memories......Page 313
10.3.2 Flip-Flops......Page 315
10.3.2.1 Flip-Flop Error Masking......Page 316
10.3.2.3 Device Model, Fault Model, and Stimulus......Page 317
10.3.2.4 Results Checking......Page 319
10.3.2.5 ASIC Case Study......Page 321
10.3.2.6 Temporal Masking Analysis......Page 322
10.3.3 Model Results......Page 323
10.4 Verifying Soft Error Performance......Page 324
10.5 Conclusions......Page 326
References......Page 327
Index......Page 328